<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/acpi/acpi_lpss.c, branch v3.12.32</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Revert "ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs"</title>
<updated>2014-01-25T16:49:28+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2014-01-17T13:23:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d2dca1c6f3ec92e9f7f42478f479cef6105fe9dc'/>
<id>d2dca1c6f3ec92e9f7f42478f479cef6105fe9dc</id>
<content type='text'>
commit 2b844ba79f4a114bd228ad6fee040ffd99a0963d upstream.

This reverts commit f6308b36c411 (ACPI: Add BayTrail SoC GPIO and LPSS
ACPI IDs), because it causes the Alan Cox' ASUS T100TA to "crash and
burn" during boot if the Baytrail pinctrl driver is compiled in.

Fixes: f6308b36c411 (ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs)
Reported-by: One Thousand Gnomes &lt;gnomes@lxorguk.ukuu.org.uk&gt;
Requested-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 2b844ba79f4a114bd228ad6fee040ffd99a0963d upstream.

This reverts commit f6308b36c411 (ACPI: Add BayTrail SoC GPIO and LPSS
ACPI IDs), because it causes the Alan Cox' ASUS T100TA to "crash and
burn" during boot if the Baytrail pinctrl driver is compiled in.

Fixes: f6308b36c411 (ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs)
Reported-by: One Thousand Gnomes &lt;gnomes@lxorguk.ukuu.org.uk&gt;
Requested-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs</title>
<updated>2014-01-09T20:25:09+00:00</updated>
<author>
<name>Paul Drews</name>
<email>paul.drews@intel.com</email>
</author>
<published>2013-11-25T22:15:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7f4f86209be7221ddb145d7059dbbfc3667c1ef0'/>
<id>7f4f86209be7221ddb145d7059dbbfc3667c1ef0</id>
<content type='text'>
commit f6308b36c411dc5afd6a6f73e6454722bfde57b7 upstream.

This adds the new ACPI ID (INT33FC) for the BayTrail GPIO
banks as seen on a BayTrail M System-On-Chip platform.  This
ACPI ID is used by the BayTrail GPIO (pinctrl) driver to
manage the Low Power Subsystem (LPSS).

Signed-off-by: Paul Drews &lt;paul.drews@intel.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit f6308b36c411dc5afd6a6f73e6454722bfde57b7 upstream.

This adds the new ACPI ID (INT33FC) for the BayTrail GPIO
banks as seen on a BayTrail M System-On-Chip platform.  This
ACPI ID is used by the BayTrail GPIO (pinctrl) driver to
manage the Low Power Subsystem (LPSS).

Signed-off-by: Paul Drews &lt;paul.drews@intel.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI / LPSS: don't crash if a device has no MMIO resources</title>
<updated>2013-09-02T10:59:40+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2013-09-02T10:30:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=af65cfe9aeae03e0682bebdf4db94582d75562dd'/>
<id>af65cfe9aeae03e0682bebdf4db94582d75562dd</id>
<content type='text'>
Intel LPSS devices that are enumerated from ACPI have both MMIO and IRQ
resources returned in their _CRS method. However, Apple Macbook Air with
Haswell has LPSS devices enumerated from PCI bus instead and _CRS method
returns only an interrupt number (but the device has _HID set that causes
the scan handler to match it).

The current ACPI / LPSS code sets pdata-&gt;dev_desc only when MMIO resource
is found for the device and in case of Macbook Air it is never found. That
leads to a NULL pointer dereference in register_device_clock().

Correct this by always setting the pdata-&gt;dev_desc.

Reported-and-tested-by: Imre Kaloz &lt;kaloz@openwrt.org&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Cc: 3.10+ &lt;stable@vger.kernel.org&gt; # 3.10+
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel LPSS devices that are enumerated from ACPI have both MMIO and IRQ
resources returned in their _CRS method. However, Apple Macbook Air with
Haswell has LPSS devices enumerated from PCI bus instead and _CRS method
returns only an interrupt number (but the device has _HID set that causes
the scan handler to match it).

The current ACPI / LPSS code sets pdata-&gt;dev_desc only when MMIO resource
is found for the device and in case of Macbook Air it is never found. That
leads to a NULL pointer dereference in register_device_clock().

Correct this by always setting the pdata-&gt;dev_desc.

Reported-and-tested-by: Imre Kaloz &lt;kaloz@openwrt.org&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Cc: 3.10+ &lt;stable@vger.kernel.org&gt; # 3.10+
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'acpi-lpss'</title>
<updated>2013-06-28T10:59:02+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2013-06-28T10:59:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f4c9f402389977dc852ef4848c7615926306735d'/>
<id>f4c9f402389977dc852ef4848c7615926306735d</id>
<content type='text'>
* acpi-lpss:
  ACPI / LPSS: override SDIO private register space size from ACPI tables
  ACPI / LPSS: mask the UART TX completion interrupt
  ACPI / LPSS: add support for Intel BayTrail

Conflicts:
	drivers/acpi/acpi_lpss.c (with commit b9e95fc)
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* acpi-lpss:
  ACPI / LPSS: override SDIO private register space size from ACPI tables
  ACPI / LPSS: mask the UART TX completion interrupt
  ACPI / LPSS: add support for Intel BayTrail

Conflicts:
	drivers/acpi/acpi_lpss.c (with commit b9e95fc)
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI / LPSS: Power up LPSS devices during enumeration</title>
<updated>2013-06-19T22:49:06+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2013-06-18T22:45:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b9e95fc65ededbec083aa91b4faa58ad992c0891'/>
<id>b9e95fc65ededbec083aa91b4faa58ad992c0891</id>
<content type='text'>
Commit 7cd8407 (ACPI / PM: Do not execute _PS0 for devices without
_PSC during initialization) introduced a regression on some systems
with Intel Lynxpoint Low-Power Subsystem (LPSS) where some devices
need to be powered up during initialization, but their device objects
in the ACPI namespace have _PS0 and _PS3 only (without _PSC or power
resources).

To work around this problem, make the ACPI LPSS driver power up
devices it knows about by using a new helper function
acpi_device_fix_up_power() that does all of the necessary
sanity checks and calls acpi_dev_pm_explicit_set() to put the
device into D0.

Reported-and-tested-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 7cd8407 (ACPI / PM: Do not execute _PS0 for devices without
_PSC during initialization) introduced a regression on some systems
with Intel Lynxpoint Low-Power Subsystem (LPSS) where some devices
need to be powered up during initialization, but their device objects
in the ACPI namespace have _PS0 and _PS3 only (without _PSC or power
resources).

To work around this problem, make the ACPI LPSS driver power up
devices it knows about by using a new helper function
acpi_device_fix_up_power() that does all of the necessary
sanity checks and calls acpi_dev_pm_explicit_set() to put the
device into D0.

Reported-and-tested-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI / LPSS: override SDIO private register space size from ACPI tables</title>
<updated>2013-06-18T23:33:37+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2013-06-18T13:51:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=958c4eb2aa325099ea1f54c7354e381e3d79f3ae'/>
<id>958c4eb2aa325099ea1f54c7354e381e3d79f3ae</id>
<content type='text'>
The SDIO device in Lynxpoint has its LTR registers reserved for a
WiFi device (a child of the SDIO device) in the ACPI namespace even
though those registers physically belong to the SDIO device itself.
In order to be able to access the SDIO LTR registers from the ACPI
LPSS driver for diagnostic purposes we need to use a size override
for the SDIO private register space.

Add a possibility to override the size of the private register space
of an LPSS device provided by the ACPI tables in the ACPI LPSS driver
and set the correct size for the SDIO device in there.

[rjw: Changelog]
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The SDIO device in Lynxpoint has its LTR registers reserved for a
WiFi device (a child of the SDIO device) in the ACPI namespace even
though those registers physically belong to the SDIO device itself.
In order to be able to access the SDIO LTR registers from the ACPI
LPSS driver for diagnostic purposes we need to use a size override
for the SDIO private register space.

Add a possibility to override the size of the private register space
of an LPSS device provided by the ACPI tables in the ACPI LPSS driver
and set the correct size for the SDIO device in there.

[rjw: Changelog]
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI / LPSS: mask the UART TX completion interrupt</title>
<updated>2013-06-18T23:31:26+00:00</updated>
<author>
<name>Heikki Krogerus</name>
<email>heikki.krogerus@linux.intel.com</email>
</author>
<published>2013-06-17T10:25:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=06d8641504726322fca54400bbac982bd44f9a27'/>
<id>06d8641504726322fca54400bbac982bd44f9a27</id>
<content type='text'>
Intel LPSS provides an extra TX byte counter and an extra TX
completion interrupt for some of its bus controllers.  However,
there is no use for the extra UART interrupt and it has to be
masked out during initialization.

Otherwise, if the firmware does not mask the interrupt and
the driver does not clear it, it may cause an interrupt flood
freezing the board to happen.

Add code masking that problematic interrupt to the ACPI LPSS driver.

[rjw: Changelog]
Signed-off-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel LPSS provides an extra TX byte counter and an extra TX
completion interrupt for some of its bus controllers.  However,
there is no use for the extra UART interrupt and it has to be
masked out during initialization.

Otherwise, if the firmware does not mask the interrupt and
the driver does not clear it, it may cause an interrupt flood
freezing the board to happen.

Add code masking that problematic interrupt to the ACPI LPSS driver.

[rjw: Changelog]
Signed-off-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI / LPSS: add support for Intel BayTrail</title>
<updated>2013-06-18T23:08:47+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2013-05-13T12:42:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f627217064dbef1eef53ceb01edb9c94203991e0'/>
<id>f627217064dbef1eef53ceb01edb9c94203991e0</id>
<content type='text'>
Intel BayTrail has almost the same Low Power Subsystem than Lynxpoint with
few differences. Peripherals are clocked with different speeds (typically
lower) and the clock is not always gated. To support this we add
possibility to share a common fixed rate clock and make clock gating
optional.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel BayTrail has almost the same Low Power Subsystem than Lynxpoint with
few differences. Peripherals are clocked with different speeds (typically
lower) and the clock is not always gated. To support this we add
possibility to share a common fixed rate clock and make clock gating
optional.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI / LPSS: register clock device for Lynxpoint DMA properly</title>
<updated>2013-05-14T04:53:58+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2013-05-08T08:55:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b59cc200ac025aca597fb21862c1c9e667f2eff2'/>
<id>b59cc200ac025aca597fb21862c1c9e667f2eff2</id>
<content type='text'>
The DMA controller in Lynxpoint is enumerated as a regular ACPI device now. To
work properly it is using the LPSS root clock as a functional clock. That's why
we have to register the clock device accordingly to the ACPI ID of the DMA
controller. The acpi_lpss.c module is responsible to do the job.

This patch also removes hardcoded name of the DMA device in clk-lpt.c and the
name of the root clock in acpi_lpss.c.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The DMA controller in Lynxpoint is enumerated as a regular ACPI device now. To
work properly it is using the LPSS root clock as a functional clock. That's why
we have to register the clock device accordingly to the ACPI ID of the DMA
controller. The acpi_lpss.c module is responsible to do the job.

This patch also removes hardcoded name of the DMA device in clk-lpt.c and the
name of the root clock in acpi_lpss.c.

Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI / LPSS: make code less confusing for reader</title>
<updated>2013-03-24T23:21:49+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2013-03-20T12:14:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=cf8df962aa830d05be1a8d5a9c7d2a67b2837b45'/>
<id>cf8df962aa830d05be1a8d5a9c7d2a67b2837b45</id>
<content type='text'>
The excerpt like this:

	if (err) {
		err = 0;
		goto error_out;
	}

makes a reader confused even if it's commented. Let's do necessary actions and
return no error explicitly.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The excerpt like this:

	if (err) {
		err = 0;
		goto error_out;
	}

makes a reader confused even if it's commented. Let's do necessary actions and
return no error explicitly.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
