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<title>linux-toradex.git/drivers/base/regmap/regmap-irq.c, branch v3.15.2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>regmap: irq: Set data pointer only on regmap_add_irq_chip success</title>
<updated>2014-03-13T21:47:36+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>k.kozlowski@samsung.com</email>
</author>
<published>2014-03-13T08:06:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=72a6a5df2c6c06e1a2504a6272d722e435a93bcb'/>
<id>72a6a5df2c6c06e1a2504a6272d722e435a93bcb</id>
<content type='text'>
After setting the 'data' pointer (wchich is returned to the caller for
freeing later) the regmap_add_irq_chip() could still fail for various
reasons (ENOMEM, regmap_read or regmap_write failure). In such case the
memory under 'data' was freed in error path and error value was returned
but the 'data' variable was not changed.

This could lead to errors if the caller passed such 'data' to
regmap_del_irq_chip().

The 'data' pointer should be changed atomically from the caller
perspective - set it only on regmap_add_irq_chip() success.

Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
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<pre>
After setting the 'data' pointer (wchich is returned to the caller for
freeing later) the regmap_add_irq_chip() could still fail for various
reasons (ENOMEM, regmap_read or regmap_write failure). In such case the
memory under 'data' was freed in error path and error value was returned
but the 'data' variable was not changed.

This could lead to errors if the caller passed such 'data' to
regmap_del_irq_chip().

The 'data' pointer should be changed atomically from the caller
perspective - set it only on regmap_add_irq_chip() success.

Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: Remove domain on exit</title>
<updated>2014-02-03T12:17:10+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-01-22T20:25:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b5ab3e5cae097642480b7983c13ff9d3ea21d0de'/>
<id>b5ab3e5cae097642480b7983c13ff9d3ea21d0de</id>
<content type='text'>
irqdomain now supports removal of domains on exit so we can properly clean
up on deletion of a regmap irqchip.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
<content type='xhtml'>
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<pre>
irqdomain now supports removal of domains on exit so we can properly clean
up on deletion of a regmap irqchip.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: Allow using zero value for ack_base</title>
<updated>2013-12-16T20:50:13+00:00</updated>
<author>
<name>Alexander Shiyan</name>
<email>shc_work@mail.ru</email>
</author>
<published>2013-12-15T09:36:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d3233433356aa1965b60b08ee61465b20e50474b'/>
<id>d3233433356aa1965b60b08ee61465b20e50474b</id>
<content type='text'>
In some cases, clear interrupt register may be at address 0.
This patch allows to use such configurations by adding additional
configuration bit to indicate this.

[With doc fix from Levente Kurusa &lt;levex@linux.com&gt; -- broonie]

Signed-off-by: Alexander Shiyan &lt;shc_work@mail.ru&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
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<pre>
In some cases, clear interrupt register may be at address 0.
This patch allows to use such configurations by adding additional
configuration bit to indicate this.

[With doc fix from Levente Kurusa &lt;levex@linux.com&gt; -- broonie]

Signed-off-by: Alexander Shiyan &lt;shc_work@mail.ru&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: clear status when disable irq</title>
<updated>2013-10-22T12:28:08+00:00</updated>
<author>
<name>Yi Zhang</name>
<email>yizhang@marvell.com</email>
</author>
<published>2013-10-22T10:44:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4bd7145b194af7cd96fc56d2ebee583b3edf03d3'/>
<id>4bd7145b194af7cd96fc56d2ebee583b3edf03d3</id>
<content type='text'>
clear the status bit if the mask register doesn't prevent
the chip level irq from being asserted

OR in the following sequence, there will be irq storm happens:
1) interrupt is triggered;
2) another thread disables it(the mask bit is set);
3) _Then_ the interrupt thread is not ACKed(the status bit is not cleared),
   and it's ignored;
4) if the irq is still asserted because of the uncleared status bit,
   the irq storm happens;

Signed-off-by: Yi Zhang &lt;yizhang@marvell.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
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<pre>
clear the status bit if the mask register doesn't prevent
the chip level irq from being asserted

OR in the following sequence, there will be irq storm happens:
1) interrupt is triggered;
2) another thread disables it(the mask bit is set);
3) _Then_ the interrupt thread is not ACKed(the status bit is not cleared),
   and it's ignored;
4) if the irq is still asserted because of the uncleared status bit,
   the irq storm happens;

Signed-off-by: Yi Zhang &lt;yizhang@marvell.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: Allow to acknowledge masked interrupts during initialization</title>
<updated>2013-07-23T19:39:12+00:00</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2013-07-22T15:15:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2753e6f8207355ab72574d48287cec187272a151'/>
<id>2753e6f8207355ab72574d48287cec187272a151</id>
<content type='text'>
In case the hardware interrupt mask register does not prevent the chip level
irq from being asserted by the corresponding interrupt status bit, already
set interrupt bits should to be cleared once after masking them during
initialization. Add a flag to let drivers enable this behavior.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In case the hardware interrupt mask register does not prevent the chip level
irq from being asserted by the corresponding interrupt status bit, already
set interrupt bits should to be cleared once after masking them during
initialization. Add a flag to let drivers enable this behavior.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: Clarify error message when we fail to request primary IRQ</title>
<updated>2013-03-19T10:50:56+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2013-03-19T10:45:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=eed456f93d01e9476a1e777d22ae8a8382546ab7'/>
<id>eed456f93d01e9476a1e777d22ae8a8382546ab7</id>
<content type='text'>
Display the name for the chip rather than just the primary IRQ so it is
clearer what exactly has failed.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Display the name for the chip rather than just the primary IRQ so it is
clearer what exactly has failed.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: call pm_runtime_put in pm_runtime_get_sync failed case</title>
<updated>2013-03-01T06:54:16+00:00</updated>
<author>
<name>Li Fei</name>
<email>fei.li@intel.com</email>
</author>
<published>2013-02-28T07:37:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=283189d3be56aa6db6f192bb255df68493cd79ac'/>
<id>283189d3be56aa6db6f192bb255df68493cd79ac</id>
<content type='text'>
Even in failed case of pm_runtime_get_sync, the usage_count
is incremented. In order to keep the usage_count with correct
value and runtime power management to behave correctly, call
pm_runtime_put(_sync) in such case.

Signed-off-by Liu Chuansheng &lt;chuansheng.liu@intel.com&gt;
Signed-off-by: Li Fei &lt;fei.li@intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Even in failed case of pm_runtime_get_sync, the usage_count
is incremented. In order to keep the usage_count with correct
value and runtime power management to behave correctly, call
pm_runtime_put(_sync) in such case.

Signed-off-by Liu Chuansheng &lt;chuansheng.liu@intel.com&gt;
Signed-off-by: Li Fei &lt;fei.li@intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: Support wake IRQ mask inversion</title>
<updated>2013-01-04T20:53:44+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2013-01-04T16:35:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9442490a02867088bcd5ed6231fa3b35a733c2b8'/>
<id>9442490a02867088bcd5ed6231fa3b35a733c2b8</id>
<content type='text'>
Support devices which have an enable rather than mask register for wake
sources.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Support devices which have an enable rather than mask register for wake
sources.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: Fix sync of wake statuses to hardware</title>
<updated>2013-01-04T20:53:43+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2013-01-04T16:32:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=33be49324f7f3e9dff10d3d07a5c78ee82f8d54e'/>
<id>33be49324f7f3e9dff10d3d07a5c78ee82f8d54e</id>
<content type='text'>
This wasn't implemented but happened to work on test systems due to lack
of wake mask inversion support.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This wasn't implemented but happened to work on test systems due to lack
of wake mask inversion support.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>regmap: irq: Use a bulk read for interrupt status where possible</title>
<updated>2013-01-04T20:53:42+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2013-01-03T14:27:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a7440eaa90cf2659920b9b28973cc1a13a2b331f'/>
<id>a7440eaa90cf2659920b9b28973cc1a13a2b331f</id>
<content type='text'>
If the interrupt status registers are a single block of registers and the
chip supports bulk reads then do a single bulk read rather than pay the
extra I/O cost. This restores the original behaviour which was lost when
support for register striding was added.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If the interrupt status registers are a single block of registers and the
chip supports bulk reads then do a single bulk read rather than pay the
extra I/O cost. This restores the original behaviour which was lost when
support for register striding was added.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
