linux-toradex.git/drivers/block/cciss_cmd.h, branch v3.10.78

cciss: use new doorbell-bit-5 reset method

2011-05-06T14:23:55+00:00

The bit-2-doorbell reset method seemed to cause (survivable) NMIs
on some systems and (unsurvivable) IOCK NMIs on some G7 servers.
Firmware guys implemented a new doorbell method to alleviate these
problems triggered by bit 5 of the doorbell register.  We want to
use it if it's available.

Signed-off-by: Stephen M. Cameron 
Signed-off-by: Jens Axboe

cciss: get rid of message related magic numbers

2011-05-06T14:23:50+00:00

Signed-off-by: Stephen M. Cameron 
Signed-off-by: Jens Axboe

cciss: do a better job of detecting controller reset failure

2011-05-06T14:23:46+00:00

Detect failure of controller reset by noticing if the 32 bytes of
"driver version" we store on the hardware in the config table
fail to get zeroed out.  Previously we noticed if the controller
did not transition to "simple mode", but this did not detect reset
failure if the controller was already in simple mode prior to
the reset attempt (e.g. due to module parameter hpsa_simple_mode=1).

Signed-off-by: Stephen M. Cameron 
Signed-off-by: Jens Axboe

cciss: Inform controller we are using 32-bit tags.

2011-03-12T09:02:16+00:00

Controller will DMA only 32-bits of the tag per command
on completion if it knows we are only using 32-bit tags.

Signed-off-by: Stephen M. Cameron 
Signed-off-by: Jens Axboe

cciss: reinstate proper FIFO order of command queue list

2011-01-10T20:50:33+00:00

Commit 8a3173de inadvertently changed the ordering when
switching to hlists. Change to regular list heads so we
can use tail list adds, this improves performance.

Signed-off-by: Jens Axboe

cciss: fix hard reset code.

2010-08-07T16:52:30+00:00

cciss: Fix hard reset code.
Smart Array controllers newer than the P600 do not honor the
PCI power state method of resetting the controllers.  Instead,
in these cases we can get them to reset via the "doorbell" register.

This escaped notice until we began using "performant" mode because
the fact that the controllers did not reset did not normally
impede subsequent operation, and so things generally appeared to
"work".  Once the performant mode code was added, if the controller
does not reset, it remains in performant mode.  The code immediately
after the reset presumes the controller is in "simple" mode
(which previously, it had remained in simple mode the whole time).
If the controller remains in performant mode any code which presumes
it is in simple mode will not work.  So the reset needs to be fixed.

Unfortunately there are some controllers which cannot be reset by
either method. (eg. p800).  We detect these cases by noticing that
the controller seems to remain in performant mode even after a
reset has been attempted.  In those cases we ignore the controller,
as any commands outstanding on it will result in stale completions.
To sum up, we try to do a better job of resetting the controller if
"reset_devices" is set, and if it doesn't work, we ignore that
controller.

Signed-off-by: Stephen M. Cameron 
Signed-off-by: Jens Axboe

cciss: change pad value from 32 to 0

2010-08-07T16:15:29+00:00

Change the command padding on 32-bit systems to 0 since setting it to 32
has the identical effect.

Signed-off-by: Mike Miller 
Cc: Stephen M. Cameron 
Signed-off-by: Andrew Morton 
Signed-off-by: Jens Axboe

cciss: add performant mode support for Stars/Sirius

2010-08-07T16:12:51+00:00

Add a mode of controller operation called Performant Mode.  Even though
cciss has been deprecated in favor of hpsa there are new controllers due
out next year that HP must support in older vendor distros.  Vendors
require all fixes/features be upstream.  These new controllers support
only 16 commands in simple mode but support up to 1024 in performant mode.
This requires us to add this support at this late date.

The performant mode transport minimizes host PCI accesses by performinf
many completions per read.  PCI writes are posted so the host can write
then immediately get off the bus not waiting for the writwe to complete to
the target.  In the context of performant mode the host read out to a
controller pulls all posted writes into host memory ensuring the reply
queue is coherent.

Signed-off-by: Mike Miller 
Cc: Stephen M. Cameron 
Signed-off-by: Andrew Morton 
Signed-off-by: Jens Axboe

cciss: detect bad alignment of scsi commands at build time

2010-02-28T18:42:31+00:00

cciss: detect bad alignment of scsi commands at build time
Incidentally fix some nearby c++ style comments.

Signed-off-by: Stephen M. Cameron 
Signed-off-by: Jens Axboe

cciss: clarify command list padding calculation

2010-02-28T18:42:31+00:00

cciss: clarify command list padding calculation

Signed-off-by: Stephen M. Cameron 
Signed-off-by: Jens Axboe