The graphics hardware modules on Tegra family of SOCs are accessed via
the host1x dma and synchronization engine. This driver exposes an
userspace interface for submitting command buffers to 2d, 3d, display
and mpe hardware modules and accessing the module register apertures
for exclusive use hardware modules.

Additional features of the driver include:
- interrupt-driven hardware module usage synchronization
- automatic clock management for hw modules
- hardware context switching for 3d registers

Change-Id: I693582249597fd307526ff3c7e35889d37406017
Reviewed-on: http://git-master/r/4091
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
Tested-by: Janne Hellsten <jhellsten@nvidia.com>

Added carveout block size properly in nvmap_split_block.
Bug 707072

Change-Id: Ie46ca482aba9f6e3231948a159144b41fe0e7c1c
Reviewed-on: http://git-master/r/3708
Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

Check if the spare buffers are contiguous before merging them.
bug 697501

Change-Id: I0987dcabefdad8fe6a1c33e63c7b19cb4a017c42
Reviewed-on: http://git-master.nvidia.com/r/3360
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

Added check for handle poison before pinning. This prevents panic
(BUG_ON in _nvmap_handle_pin_locked) when trying to pin already freed
handle.

Bug 684375

Change-Id: I85ba4b37b2f193c19782edeaa562b7f77915cfc4
Reviewed-on: http://git-master/r/2478
Tested-by: Anssi Kalliolahti <akalliolahti@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

nvmap shouldn't require MACH_TEGRA_GENERIC; it should be buildable
(sans NvRm APIs or NvOs preserved memory handle bootargs) in a stock
kernel. move the NvOs and NvRm dependencies to ifdef'd source code,
rather than Kconfigs

Change-Id: I11d4049460975bc9f2bf779c4c2fa6c7a8747583
Reviewed-on: http://git-master/r/1807
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>

_nvmap_handle_unpin needs to acquire the mru_vma_lock before decrementing
the pin count, to ensure that a decrement to zero and insertion on the
MRU VMA list appears atomic with respect to a second client calling
_nvmap_handle_pin on the same handle; otherwise, the two clients race
and the pin operation may trigger a BUG because the handle has a valid
IOVMM area but is not located on any MRU VMA list.

also, clean up some additional allocation-inside-spinlock issues;
release the MRU VMA lock before calling tegra_iovmm_create_vm, and
reacquire the lock after returning.

Change-Id: I6703d21266124b3084f10f5b94a12cdeaf43a330

statically allocate a maximally-sized block array at heap init time,
rather than dynamically doubling the array size when spare blocks are
unavailable.

allocate new handle ref objects prior to locking the file's ref lock

Change-Id: I193210e059ed38c67287650fc4b578e85097ec12

add power rail support to GPIO driver

Change-Id: I45d4c1110a635047d68fb14f3e72a28f99acbe1b

Change-Id: I65e85fd069317e628b121c792df95f329aac9a3d