linux-toradex.git/drivers/clk/berlin, branch v4.2.2

Merge tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2015-07-02T02:22:00+00:00

Pull clock framework updates from Michael Turquette:
 "The changes to the common clock framework for 4.2 are dominated by new
  drivers and updates to existing ones, as usual.

  There are some fixes to the framework itself and several cleanups for
  sparse warnings, etc"

* tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
  clk: stm32: Add clock driver for STM32F4[23]xxx devices
  dt-bindings: Document the STM32F4 clock bindings
  cpufreq: exynos: remove Exynos4210 specific cpufreq driver support
  ARM: Exynos: switch to using generic cpufreq driver for Exynos4210
  clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock
  clk: samsung: add infrastructure to register cpu clocks
  clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support
  doc: dt: add documentation for lpc1850-ccu clk driver
  clk: add lpc18xx ccu clk driver
  doc: dt: add documentation for lpc1850-cgu clk driver
  clk: add lpc18xx cgu clk driver
  clk: keystone: add support for post divider register for main pll
  clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSED
  clk: cygnus: remove Cygnus dummy clock binding
  clk: cygnus: add clock support for Broadcom Cygnus
  clk: Change bcm clocks build dependency
  clk: iproc: add initial common clock support
  clk: iproc: define Broadcom iProc clock binding
  MAINTAINERS: update email for Michael Turquette
  clk: meson: add some error handling in meson_clk_register_cpu()
  ...

clk: berlin: drop direct of_iomap of nodes reg property

2015-05-18T16:10:13+00:00

The Berlin clock driver was sharing a DT node with the pin controller
and the reset driver. All these devices are now sub-nodes of the chip
controller. This patch rework the Berlin clock driver to allow moving
the Berlin clock DT bindings into their own sub-node of the chip
controller node.

Signed-off-by: Antoine Tenart 
Acked-by: Stephen Boyd 
Signed-off-by: Sebastian Hesselbarth

clk: berlin: prepare simple-mfd conversion

2015-05-18T16:10:09+00:00

Prepare conversion of berlin clk drivers to a simple-mfd sub-node by
checking for parent node compatible. If parent node is "syscon" compatible
use it for of_iomap instead of the own node.

Signed-off-by: Antoine Tenart 
Acked-by: Stephen Boyd 
Signed-off-by: Sebastian Hesselbarth

clk: berlin: Silence sparse warning

2015-05-15T00:11:21+00:00

drivers/clk/berlin/berlin2-pll.c:94:12: warning: symbol 'berlin2_pll_register' was not declared. Should it be static?

Cc: Alexandre Belloni 
Acked-by: Sebastian Hesselbarth 
Signed-off-by: Stephen Boyd

clk: berlin: bg2q: remove non-exist "smemc" gate clock

2015-01-13T18:58:43+00:00

The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.

Signed-off-by: Jisheng Zhang 
Cc: stable@vger.kernel.org # 3.16+
Signed-off-by: Michael Turquette

clk: berlin: add core clock driver for BG2Q

2014-05-29T16:30:19+00:00

This driver deals with the core clocks found on Marvell Berlin BG2Q. For the
shared register dividers, make use of the corresponding driver and add some
single clock muxes and gates for the rest.

Signed-off-by: Alexandre Belloni 
Signed-off-by: Mike Turquette

clk: berlin: add core clock driver for BG2/BG2CD

2014-05-29T16:30:19+00:00

This driver deals with the core clocks found on Marvell Berlin
BG2 and BG2CD. For the shared register dividers, make use of the
corresponding driver and add some single clock muxes and gates for
the rest.

Signed-off-by: Sebastian Hesselbarth 
Acked-by: Alexandre Belloni 
Signed-off-by: Mike Turquette

clk: berlin: add driver for BG2x complex divider cells

2014-05-29T16:30:18+00:00

This is a driver for the complex divider cells found on Marvell Berlin2
SoCs. The cells come in two flavors: single register cells and shared
register cells.

Signed-off-by: Alexandre Belloni 
Signed-off-by: Sebastian Hesselbarth 
Signed-off-by: Mike Turquette

clk: berlin: add driver for BG2x simple PLLs

2014-05-29T16:30:17+00:00

This is a clock driver for the simple PLLs found on Berlin SoCs.
With repect to PLL registers and features, BG2/BG2CD and BG2Q are
slightly different, e.g. different allowed VCO dividers and bit
shifts.

Signed-off-by: Alexandre Belloni 
Signed-off-by: Sebastian Hesselbarth 
Signed-off-by: Mike Turquette

clk: berlin: add driver for BG2x audio/video PLL

2014-05-29T16:30:16+00:00

This is a driver for the AVPLLs built upon a VCO with 8 channels each
found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share
the same register set, sometimes registers shifts for one of the VCOs
are a bit off. Nothing serious that should require a separate driver,
so deal with both VCOs in a single driver instead.

Signed-off-by: Alexandre Belloni 
Signed-off-by: Sebastian Hesselbarth 
Signed-off-by: Mike Turquette