linux-toradex.git/drivers/clk/clk-composite.c, branch v3.17.4

clk: composite: improve rate_hw sanity check logic

2014-07-13T19:17:05+00:00

The function pointer population and sanity checking logic got a bit ugly
with the advent of the .determine_rate callback. Clean it up.

Signed-off-by: Mike Turquette

clk: composite: allow read-only clocks

2014-07-13T19:17:04+00:00

This allows readl-only composite clocks by making mux_ops->set_parent and
divider_ops->round_rate/set_rate optional.

Signed-off-by: Heiko Stuebner 
Acked-By: Max Schwarz 
Tested-By: Max Schwarz 
Signed-off-by: Mike Turquette

clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent

2014-07-13T19:16:08+00:00

In case the rate_hw does not implement determine_rate, but only round_rate
we fallback to best_parent selection if mux_hw is present and support
reparenting.

This also fixes a rate calculation problem when using the standard div and
mux ops, as in this case currently only the mux->determine_rate is used
in the composite rate calculation.
So when for example the composite clock has two parents at 600 and 800MHz,
the requested rate is 75MHz, which the divider could provide, without this
change the rate would be set 600MHz ignoring the divider completely.
This may be way out of spec for the component.

Signed-off-by: Boris BREZILLON 
Signed-off-by: Heiko Stuebner 
[heiko@sntech.de: fixed output return a rate instead of the diff]
Acked-By: Max Schwarz 
Tested-By: Max Schwarz 
Tested-by: Gabriel Fernandez 
Signed-off-by: Mike Turquette

clk: composite: pass mux_hw into determine_rate

2014-01-15T15:48:03+00:00

The composite clock's .determine_rate implementation can call the
underyling .determine_rate callback corresponding to rate_hw or the
underlying .determine_rate callback corresponding to mux_hw. In both
cases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into
the correct callback.

Reported-by: Lemon Dai 
Signed-off-by: Mike Turquette

clk: composite: .determine_rate support

2013-11-10T10:39:07+00:00

This commit adds .determine_rate support to the composite clock. It will
use the .determine_rate callback from the rate component if available,
and fall back on the mux component otherwise. This allows composite
clocks to enjoy the benefits of automatic clock reparenting.

Signed-off-by: Emilio López 
Signed-off-by: Maxime Ripard

clk: composite: allow fixed rates & fixed dividers

2013-04-12T18:23:24+00:00

The composite clock assumes that any clock implementing the .recalc_rate
callback will also implement .round_rate and .set_rate.  This is not
always true; the basic fixed-rate clock will only implement .recalc_rate
and a fixed-divider clock may choose to implement .recalc_rate and
.round_rate but not .set_rate.

Fix this by conditionally registering .round_rate and .set_rate
callbacks based on the rate_ops passed in to clk_composite_register.

Signed-off-by: Mike Turquette 
Cc: Prashant Gaikwad 
Tested-by: Emilio López 
Cc: Gregory CLEMENT

clk: composite: rename 'div' references to 'rate'

2013-04-12T18:22:35+00:00

Rename all div_hw and div_ops related variables and functions to use
rate_hw, rate_ops, etc.  This is to make the rate-change portion of the
composite clk implementation more generic.  A patch following this one
will allow for fixed-rate clocks to reuse this infrastructure.

Signed-off-by: Mike Turquette 
Reviewed-by: Prashant Gaikwad 
Tested-by: Emilio López 
Cc: Gregory CLEMENT

clk: Add composite clock type

2013-03-26T19:51:48+00:00

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
Signed-off-by: Mike Turquette