linux-toradex.git/drivers/clk/clk-divider.c, branch v4.2.2

clk: basic-types: Remove useless allocation failure printks

2015-05-14T23:51:50+00:00

Printing an error on kmalloc() failures is unnecessary. Remove
the print and use *ptr in sizeof() for future-proof code.

Signed-off-by: Stephen Boyd

clk: divider: fix calculation of initial best divider when rounding to closest

2015-03-09T21:20:17+00:00

Similar to the reasoning for the previous commit

	DIV_ROUND_CLOSEST(parent_rate, rate)

might not be the best integer divisor to get a good approximation for
rate from parent_rate (given the metric for CLK_DIVIDER_ROUND_CLOSEST).

For example assume a parent rate of 1000 Hz and a target rate of 700.
Using DIV_ROUND_CLOSEST the suggested divisor gets calculated to 1
resulting in a target rate of 1000 with a delta of 300 to the desired
rate. With choosing 2 as divisor however the resulting rate is 500 which
is nearer to 700.

Signed-off-by: Uwe Kleine-König 
Acked-by: Sascha Hauer 
Acked-by: Maxime Coquelin 
Signed-off-by: Michael Turquette

clk: divider: fix selection of divider when rounding to closest

2015-03-09T21:19:54+00:00

It's an invalid approach to assume that among two divider values
the one nearer the exact divider is the better one.

Assume a parent rate of 1000 Hz, a divider with CLK_DIVIDER_POWER_OF_TWO
and a target rate of 89 Hz. The exact divider is ~ 11.236 so 8 and 16
are the candidates to choose from yielding rates 125 Hz and 62.5 Hz
respectivly. While 8 is nearer to 11.236 than 16 is, the latter is still
the better divider as 62.5 is nearer to 89 than 125 is.

Fixes: 774b514390b1 (clk: divider: Add round to closest divider)
Signed-off-by: Uwe Kleine-König 
Acked-by: Sascha Hauer 
Acked-by: Maxime Coquelin 
Signed-off-by: Michael Turquette

clk: divider: fix calculation of maximal parent rate for a given divider

2015-03-09T21:19:27+00:00

The rate provided at the output of a clk-divider is calculated as:

	DIV_ROUND_UP(parent_rate, div)

since commit b11d282dbea2 (clk: divider: fix rate calculation for
fractional rates). So to yield a rate not bigger than r parent_rate
must be <= r * div.

The effect of choosing a parent rate that is too big as was done before
this patch results in wrongly ruling out good dividers.

Note that this is not a complete fix as __clk_round_rate might return a
value >= its 2nd parameter. Also for dividers with
CLK_DIVIDER_ROUND_CLOSEST set the calculation is not accurate. But this
fixes the test case by Sascha Hauer that uses a chain of three dividers
under a fixed clock.

Fixes: b11d282dbea2 (clk: divider: fix rate calculation for fractional rates)
Suggested-by: Sascha Hauer 
Signed-off-by: Uwe Kleine-König 
Acked-by: Sascha Hauer 
Signed-off-by: Michael Turquette

clk: divider: return real rate instead of divider value

2015-03-06T17:25:13+00:00

Commit bca9690b9426 ("clk: divider: Make generic for usage elsewhere")
returned only the divider value for read-only dividers instead of the
actual rate.

Fixes: bca9690b9426 ("clk: divider: Make generic for usage elsewhere")
Signed-off-by: Heiko Stuebner 
Reviewed-by: James Hogan 
Tested-by: James Hogan 
Acked-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: divider: Make generic for usage elsewhere

2015-01-27T19:48:52+00:00

Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.

Signed-off-by: Stephen Boyd 
Tested-by: Kenneth Westfield 
Signed-off-by: Michael Turquette

clk: Add clk_unregister_{divider, gate, mux} to close memory leak

2015-01-17T21:52:41+00:00

The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.

Add corresponding unregister functions which will release all resources.

Signed-off-by: Krzysztof Kozlowski 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk-divider: Fix READ_ONLY when divider > 1

2014-11-17T19:13:52+00:00

Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.

However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.

Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.

For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.

Signed-off-by: James Hogan 
Cc: Thomas Abraham 
Cc: Tomasz Figa 
Cc: Max Schwarz 
Cc:  # v3.16+
Acked-by: Haojian Zhuang 
Signed-off-by: Michael Turquette

clk: divider: Fix overflow in clk_divider_bestdiv

2014-05-28T02:16:24+00:00

Commit c686078 ("clk: divider: Add round to closest divider") introduced
a helper function to check whether given divisor is the best one instead
of direct check. However due to int type used instead of unsigned long
for passing calculated rates to this function in certain cases an
overflow could occur, for example when trying to obtain maximum possible
clock rate by calling clk_round_rate(..., UINT_MAX).

This patch fixes this issue by changing the type of rate, now and best
arguments of the function to unsigned long, which is the type that
should be used for clock rates.

Signed-off-by: Tomasz Figa 
Acked-by: Maxime Coquelin 
Signed-off-by: Mike Turquette

Merge branch 'clk-fixes' into clk-next

2014-05-23T21:37:10+00:00