linux-toradex.git/drivers/clk/clk-divider.c, branch v4.9.67

clk: divider: Fix clk_divider_round_rate() to use clk_readl()

2016-08-13T00:33:09+00:00

clk-divider uses clk_readl()/clk_writel() everywhere, except in
clk_divider_round_rate(), where plain readl() is used. Change this to
clk_readl(), as it makes a difference on powerpc.

Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: James Hogan 
Signed-off-by: Stephen Boyd

clk: divider: Add hw based registration APIs

2016-04-19T23:55:01+00:00

Add registration APIs in the clk divider code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd

clk: optimize the divider walk in clk_divider_bestdiv()

2016-01-30T00:45:32+00:00

Because _next_div() returns a valid divider, there is no need to
consult _is_valid_div() for the validity of the divider in every
iteration.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h

2016-01-29T20:59:50+00:00

to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.

Signed-off-by: Geliang Tang 
Signed-off-by: Stephen Boyd

clk-divider: make sure read-only dividers do not write to their register

2016-01-29T20:44:37+00:00

Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.

On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.

To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.

The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.

Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

clk: divider: Cap table divider values to 'width' member

2015-12-01T02:24:20+00:00

When we use a clk divider with a divider table, we limit the
maximum divider value in divider_get_val() to the
div_mask(width), but when we calculate the divider in
divider_round_rate() we don't consider that the maximum divider
may be limited by the width. Pass the width along to
_get_table_maxdiv() so that we only return the maximum divider
that is valid. This is useful for clocks that want to share the
same divider table while limiting the available dividers to some
subset of the table depending on the width of the bitfield.

Cc: Rajendra Nayak 
Signed-off-by: Stephen Boyd

clk: divider: handle integer overflow when dividing large clock rates

2015-09-16T22:22:33+00:00

On 32-bit architectures, 'unsigned long' (the type used to hold clock
rates, in Hz) is often only 32 bits wide. DIV_ROUND_UP() (as used in,
e.g., commit b11d282dbea2 "clk: divider: fix rate calculation for
fractional rates") can yield an integer overflow on clock rates that are
not (by themselves) too large to fit in 32 bits, because it performs
addition before the division. See for example:

  DIV_ROUND_UP(3000000000, 1500000000) = (3.0G + 1.5G - 1) / 1.5G
                                       = OVERFLOW / 1.5G

This patch fixes such cases by always promoting the dividend to 64-bits
(unsigned long long) before doing the division. While this patch does
not resolve the issue with large clock rates across the common clock
framework nor address the problems with doing full 64-bit arithmetic on
a 32-bit architecture, it does fix some issues seen when using clock
dividers on a 3GHz reference clock to produce a 1.5GHz CPU clock for an
ARMv7 Brahma B15 SoC.

Signed-off-by: Brian Norris 
Reference: http://lkml.kernel.org/g/20150413201433.GQ32500@ld-irv-0074
Signed-off-by: Stephen Boyd

clk: Convert basic types to clk_hw based provider APIs

2015-08-24T23:48:48+00:00

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Signed-off-by: Stephen Boyd

clk: Convert __clk_get_flags() to clk_hw_get_flags()

2015-08-24T23:48:44+00:00

Mostly converted with the following snippet:

@@
struct clk_hw *E;
@@

-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)

Acked-by: Tero Kristo 
Cc: Maxime Ripard 
Cc: Max Filippov 
Acked-by: Sebastian Hesselbarth 
Cc: Daniel Thompson 
Cc: Coquelin 
Signed-off-by: Stephen Boyd

clk: basic-type: Silence warnings about lock imbalances

2015-07-28T18:59:28+00:00

The basic clock types use conditional locking for the register
accessor spinlocks. Add __acquire() and __release() markings in
the right locations so that sparse isn't tripped up on the
conditional locking.

drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block
drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block
drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block

Cc: Andy Shevchenko 
Signed-off-by: Stephen Boyd