linux-toradex.git/drivers/clk/clk-versaclock3.c, branch v7.0-rc2

clk: versaclock3: convert from divider_round_rate() to divider_determine_rate()

2026-01-22T15:48:26+00:00

The divider_round_rate() function is now deprecated, so let's migrate
to divider_determine_rate() instead so that this deprecated API can be
removed.

Note that when the main function itself was migrated to use
determine_rate, this was mistakenly converted to:

    req->rate = divider_round_rate(...)

This is invalid in the case when an error occurs since it can set the
rate to a negative value.

Fixes: 9e3372b2ebac ("clk: versaclock3: convert from round_rate() to determine_rate()")
Signed-off-by: Brian Masney

clk: versaclock3: convert from round_rate() to determine_rate()

2025-09-08T13:41:29+00:00

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney

clk: versaclock3: Add support for the 5L35023 variant

2024-12-10T22:49:29+00:00

Add support for the 5L35023 variant of the Versa 3 clock generator.

Reviewed-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/20241210170953.2936724-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Stephen Boyd

clk: versaclock3: Prepare for the addition of 5L35023 device

2024-12-10T22:49:24+00:00

The 5P35023 and 5L35035 Versa 3 clock generator variants are different but
the versaclock3 driver could be used with small adjustments. The features
that are implemented in driver and differs b/w variants are the PLL2 Fvco
and clock sel bit for SE2 clock. Adjust the driver to prepare for the
addition of 5L35023 device.

Reviewed-by: Biju Das 
Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/20241210170953.2936724-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Stephen Boyd

clk: versaclock3: Drop ret variable

2023-12-17T23:56:14+00:00

Drop ret variable from vc3_clk_mux_determine_rate().

While at it, return the value returned by regmap_*
wherever possible instead of returning 0.

Signed-off-by: Biju Das 
Link: https://lore.kernel.org/r/20231122142310.203169-6-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd

clk: versaclock3: Add missing space between ')' and '{'

2023-12-17T23:56:14+00:00

Add missing space between ')' and '{' for hw.init initialization.

While at it, update the macro VC3_PLL1_LOOP_FILTER_N_DIV_MSB
0x0a->0xa.

Signed-off-by: Biju Das 
Link: https://lore.kernel.org/r/20231122142310.203169-5-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd

clk: versaclock3: Use u8 return type for get_parent() callback

2023-12-17T23:56:14+00:00

The return type of get_parent() member in struct clk_ops is u8.
Use same return type for corresponding callback function as well.

Signed-off-by: Biju Das 
Link: https://lore.kernel.org/r/20231122142310.203169-4-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd

clk: versaclock3: Avoid unnecessary padding

2023-12-17T23:56:14+00:00

Move long/pointer variables at the beginning of struct to avoid
unnecessary padding.

Signed-off-by: Biju Das 
Link: https://lore.kernel.org/r/20231122142310.203169-3-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd

clk: versaclock3: Update vc3_get_div() to avoid divide by zero

2023-12-17T23:56:14+00:00

Update vc3_get_div() to avoid divide by zero operation on
vc3_div_round_rate() by returning1, if there is no table match
found.

Signed-off-by: Biju Das 
Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd

Merge branches 'clk-renesas', 'clk-kunit', 'clk-regmap' and 'clk-frac-divider' into clk-next

2023-10-30T21:12:20+00:00

 - Make clk kunit tests work with lockdep
 - Fix clk gate kunit test for big-endian
 - Convert more than a handful of clk drivers to use regmap maple tree
 - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
   implementation

* clk-renesas: (23 commits)
  clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
  clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
  clk: renesas: Add minimal boot support for RZ/G3S SoC
  clk: renesas: rzg2l: Add divider clock for RZ/G3S
  clk: renesas: rzg2l: Refactor SD mux driver
  clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
  clk: renesas: rzg2l: Add struct clk_hw_data
  clk: renesas: rzg2l: Add support for RZ/G3S PLL
  clk: renesas: rzg2l: Remove critical area
  clk: renesas: rzg2l: Fix computation formula
  clk: renesas: rzg2l: Trust value returned by hardware
  clk: renesas: rzg2l: Lock around writes to mux register
  clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
  clk: renesas: rcar-gen3: Extend SDnH divider table
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
  clk: renesas: r8a7795: Constify r8a7795_*_clks
  clk: renesas: r9a06g032: Name anonymous structs
  clk: renesas: r9a06g032: Fix kerneldoc warning
  clk: renesas: rzg2l: Use u32 for flag and mux_flags
  clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
  ...

* clk-kunit:
  clk: Fix clk gate kunit test on big-endian CPUs
  clk: Parameterize clk_leaf_mux_set_rate_parent
  clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops

* clk-regmap:
  clk: versaclock7: Convert to use maple tree register cache
  clk: versaclock5: Convert to use maple tree register cache
  clk: versaclock3: Convert to use maple tree register cache
  clk: versaclock3: Remove redundant _is_writeable()
  clk: si570: Convert to use maple tree register cache
  clk: si544: Convert to use maple tree register cache
  clk: si5351: Convert to use maple tree register cache
  clk: si5341: Convert to use maple tree register cache
  clk: si514: Convert to use maple tree register cache
  clk: cdce925: Convert to use maple tree register cache

* clk-frac-divider:
  clk: fractional-divider: tests: Add test suite for edge cases
  clk: fractional-divider: Improve approximation when zero based and export