linux-toradex.git/drivers/clk/imx, branch v5.0

clk: imx: Fix fractional clock set rate computation

2019-01-24T19:17:28+00:00

Before multiplying by PLL_FRAC_DENOM, the temp64 needs to be
 temp64 = rate * 2 - divfi * parent_rate * 8, instead of:
 temp64 = (rate * 2 - divfi) * parent_rate

Fixes: 6209624b9a5c1e ("clk: imx: Add fractional PLL output clock")
Signed-off-by: Abel Vesa 
Signed-off-by: Stephen Boyd

clk: imx: fix potential NULL dereference in imx8qxp_lpcg_clk_probe()

2019-01-09T18:34:54+00:00

platform_get_resource() may fail and return NULL, so we should
better check it's return value to avoid a NULL pointer dereference
a bit later in the code.

This is detected by Coccinelle semantic patch.

@@
expression pdev, res, n, t, e, e1, e2;
@@

res = platform_get_resource(pdev, t, n);
+ if (!res)
+   return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);

Fixes: 1e3121bfe51a ("clk: imx: add imx8qxp lpcg driver")
Signed-off-by: Wei Yongjun 
Reviewed-by: Dong Aisheng 
Signed-off-by: Stephen Boyd

clk: imx8qxp: make the name of clock ID generic

2018-12-28T18:43:57+00:00

SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs.
Let's make the name of clock ID generic to allow other SoCs to reuse
the common part.

This patch only changes the clock id name and file name, so no
functional change.

Cc: Stephen Boyd 
Cc: Rob Herring 
Cc: Shawn Guo 
Cc: Sascha Hauer 
Cc: Fabio Estevam 
Cc: Michael Turquette 
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng 
Reviewed-by: Fabio Estevam 
Reviewed-by: Rob Herring 
Signed-off-by: Stephen Boyd

Merge branch 'clk-imx7ulp' into clk-next

2018-12-14T22:03:38+00:00

* clk-imx7ulp:
  clk: imx: imx7ulp: add arm hsrun mode clocks support
  dt-bindings: clock: imx7ulp: add HSRUN mode related clocks

clk: imx: imx7ulp: add arm hsrun mode clocks support

2018-12-14T22:03:12+00:00

i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
or HSRUN mode, it is controlled in SMC1 module. The RUN
mode and HSRUN mode will use different clock source for
ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
mode, so the control bits in SMC1 module can be abstracted
as a HW clock mux, this patch adds HSRUN mode related
clocks in SCG1 module and adds "arm" clock in SMC1 module
to support RUN mode and HSRUN mode switch.

Latest clock tree in RUN mode as below:

 firc                                 0        0        0    48000000          0     0  50000
    firc_bus_clk                      0        0        0    48000000          0     0  50000
    hsrun_scs_sel                     0        0        0    48000000          0     0  50000
       hsrun_divcore                  0        0        0    48000000          0     0  50000

 sosc                                 3        3        3    24000000          0     0  50000
    spll_pre_sel                      1        1        1    24000000          0     0  50000
       spll_pre_div                   1        1        2    24000000          0     0  50000
          spll                        1        1        2   528000000          0     0  50000
             spll_pfd0                1        1        1   500210526          0     0  50000
                spll_pfd_sel          1        1        0   500210526          0     0  50000
                   spll_sel           1        1        0   500210526          0     0  50000
                      scs_sel         1        1        0   500210526          0     0  50000
                         divcore      1        1        0   500210526          0     0  50000
                            arm       1        1        0   500210526          0     0  50000

Signed-off-by: Anson Huang 
Signed-off-by: Stephen Boyd

Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next

2018-12-14T21:34:47+00:00

 - NXP i.MX7ULP SoC clock support
 - Support for i.MX8QXP SoC clocks
 - Support for NXP i.MX8MQ clock controllers

* clk-imx7ulp:
  clk: imx: add imx7ulp clk driver
  clk: imx: implement new clk_hw based APIs
  clk: imx: make mux parent strings const
  dt-bindings: clock: add imx7ulp clock binding doc
  clk: imx: add imx7ulp composite clk support
  clk: imx: add pfdv2 support
  clk: imx: add pllv4 support
  clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
  clk: imx: add gatable clock divider support

* clk-imx6-fixes:
  clk: imx6q: handle ENET PLL bypass
  clk: imx6q: optionally get CCM inputs via standard clock handles
  clk: imx6q: reset exclusive gates on init

* clk-imx-fixes:
  clk: imx6q: add DCICx clocks gate
  clk: imx6sl: ensure MMDC CH0 handshake is bypassed
  clk: imx7d: remove UART1 clock setting

* clk-imx8qxp:
  clk: imx: add imx8qxp lpcg driver
  clk: imx: add lpcg clock support
  clk: imx: add imx8qxp clk driver
  clk: imx: add scu clock common part
  clk: imx: add configuration option for mmio clks
  dt-bindings: clock: add imx8qxp lpcg clock binding
  dt-bindings: clock: imx8qxp: add SCU clock IDs
  firmware: imx: add pm svc headfile
  dt-bindings: fsl: scu: update power domain binding
  firmware: imx: remove resource id enums
  dt-bindings: imx: add scu resource id headfile

* clk-imx8mq:
  clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant
  clk: imx: remove redundant initialization of ret to zero
  clk: imx: Add SCCG PLL type
  clk: imx: Add fractional PLL output clock
  clk: imx: Add clock driver for i.MX8MQ CCM
  clk: imx: Add imx composite clock
  dt-bindings: Add binding for i.MX8MQ CCM

clk: imx: add imx8qxp lpcg driver

2018-12-14T21:01:14+00:00

Add imx8qxp lpcg driver support

Cc: Stephen Boyd 
Cc: Shawn Guo 
Cc: Sascha Hauer 
Cc: Fabio Estevam 
Cc: Michael Turquette 
Signed-off-by: Dong Aisheng 
Signed-off-by: Stephen Boyd

clk: imx: add lpcg clock support

2018-12-14T21:00:51+00:00

The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
And they're bedind the SCU clock.

Cc: Stephen Boyd 
Cc: Shawn Guo 
Cc: Sascha Hauer 
Cc: Fabio Estevam 
Cc: Michael Turquette 
Signed-off-by: Dong Aisheng 
Signed-off-by: Stephen Boyd

clk: imx: add imx8qxp clk driver

2018-12-14T21:00:29+00:00

Add imx8qxp clk driver which is based on SCU firmware clock service.

Cc: Shawn Guo 
Cc: Sascha Hauer 
Cc: Fabio Estevam 
Cc: Stephen Boyd 
Cc: Michael Turquette 
Signed-off-by: Dong Aisheng 
[sboyd@kernel.org: Move the makefile rule higher in the file]
Signed-off-by: Stephen Boyd

clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant

2018-12-14T20:56:27+00:00

Remove the dependency between the i.MX8MQ CCM clock driver
and the CONFIG_SOC_IMX8MQ and use CONFIG_CLK_IMX8MQ instead.
CONFIG_CLK_IMX8MQ depends on ARCH_MXC && ARM64.

Signed-off-by: Abel Vesa 
Signed-off-by: Stephen Boyd