<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/clk/imx, branch v6.12-rc1</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>clk: Switch back to struct platform_driver::remove()</title>
<updated>2024-09-21T21:12:05+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@baylibre.com</email>
</author>
<published>2024-09-09T14:40:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f00b45db02ae4e0288bb719a9935b966733c7e91'/>
<id>f00b45db02ae4e0288bb719a9935b966733c7e91</id>
<content type='text'>
After commit 0edb555a65d1 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.

Convert all clk drivers to use .remove(), with the eventual goal to drop
struct platform_driver::remove_new(). As .remove() and .remove_new() have
the same prototypes, conversion is done by just changing the structure
member name in the driver initializer.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@baylibre.com&gt;
Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com
Acked-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt; # renesas
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
After commit 0edb555a65d1 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.

Convert all clk drivers to use .remove(), with the eventual goal to drop
struct platform_driver::remove_new(). As .remove() and .remove_new() have
the same prototypes, conversion is done by just changing the structure
member name in the driver initializer.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@baylibre.com&gt;
Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com
Acked-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt; # renesas
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'clk-imx-old' into clk-imx</title>
<updated>2024-09-05T18:30:59+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@kernel.org</email>
</author>
<published>2024-09-05T18:30:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a09e3cf770bcffa40f22cc2f0f4d24a84f937f26'/>
<id>a09e3cf770bcffa40f22cc2f0f4d24a84f937f26</id>
<content type='text'>
* clk-imx: (22 commits)
  clk: imx: composite-7ulp: Use NULL instead of 0
  clk: imx: add missing MODULE_DESCRIPTION() macros
  clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
  clk: imx: fracn-gppll: update rate table
  clk: imx: imx8qxp: Parent should be initialized earlier than the clock
  clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
  clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
  clk: imx: imx8qxp: Add LVDS bypass clocks
  clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
  clk: imx: imx8mn: add sai7_ipg_clk clock settings
  clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
  clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
  clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
  clk: imx: fracn-gppll: fix fractional part of PLL getting lost
  clk: imx: composite-7ulp: Check the PCC present bit
  clk: imx: composite-93: keep root clock on when mcore enabled
  clk: imx: composite-8m: Enable gate clk with mcore_booted
  clk: imx: imx6ul: fix default parent for enet*_ref_sel
  clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll
  clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* clk-imx: (22 commits)
  clk: imx: composite-7ulp: Use NULL instead of 0
  clk: imx: add missing MODULE_DESCRIPTION() macros
  clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
  clk: imx: fracn-gppll: update rate table
  clk: imx: imx8qxp: Parent should be initialized earlier than the clock
  clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
  clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
  clk: imx: imx8qxp: Add LVDS bypass clocks
  clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
  clk: imx: imx8mn: add sai7_ipg_clk clock settings
  clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
  clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
  clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
  clk: imx: fracn-gppll: fix fractional part of PLL getting lost
  clk: imx: composite-7ulp: Check the PCC present bit
  clk: imx: composite-93: keep root clock on when mcore enabled
  clk: imx: composite-8m: Enable gate clk with mcore_booted
  clk: imx: imx6ul: fix default parent for enet*_ref_sel
  clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll
  clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL</title>
<updated>2024-09-04T09:39:38+00:00</updated>
<author>
<name>Michel Alex</name>
<email>Alex.Michel@wiedemann-group.com</email>
</author>
<published>2024-09-02T09:05:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=32c055ef563c3a4a73a477839f591b1b170bde8e'/>
<id>32c055ef563c3a4a73a477839f591b1b170bde8e</id>
<content type='text'>
Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add
ethernet refclock mux support") sets the internal clock as default
ethernet clock.

Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL,
the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct
parent and shall be used instead.
Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M
is the correct parent.

Cc: stable@vger.kernel.org
Signed-off-by: Alex Michel &lt;alex.michel@wiedemann-group.com&gt;
Reviewed-by: Oleksij Rempel &lt;o.rempel@pengutronix.de&gt;
Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add
ethernet refclock mux support") sets the internal clock as default
ethernet clock.

Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL,
the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct
parent and shall be used instead.
Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M
is the correct parent.

Cc: stable@vger.kernel.org
Signed-off-by: Alex Michel &lt;alex.michel@wiedemann-group.com&gt;
Reviewed-by: Oleksij Rempel &lt;o.rempel@pengutronix.de&gt;
Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx95: enable the clock of NETCMIX block control</title>
<updated>2024-08-29T07:02:18+00:00</updated>
<author>
<name>Wei Fang</name>
<email>wei.fang@nxp.com</email>
</author>
<published>2024-08-29T01:18:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=42dc425fa8b5be982bcc2025d5bf30be8b26da86'/>
<id>42dc425fa8b5be982bcc2025d5bf30be8b26da86</id>
<content type='text'>
The NETCMIX block control consists of registers for configuration of
peripherals in the NETC domain, so enable the clock of NETCMIX to
support the configuration.

Signed-off-by: Wei Fang &lt;wei.fang@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Link: https://lore.kernel.org/r/20240829011849.364987-4-wei.fang@nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The NETCMIX block control consists of registers for configuration of
peripherals in the NETC domain, so enable the clock of NETCMIX to
support the configuration.

Signed-off-by: Wei Fang &lt;wei.fang@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Link: https://lore.kernel.org/r/20240829011849.364987-4-wei.fang@nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data</title>
<updated>2024-08-29T07:01:02+00:00</updated>
<author>
<name>Shengjiu Wang</name>
<email>shengjiu.wang@nxp.com</email>
</author>
<published>2024-07-10T08:41:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=35121e9def072aaa2361572829e4f71f80dd6e8d'/>
<id>35121e9def072aaa2361572829e4f71f80dd6e8d</id>
<content type='text'>
"acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM
driver, but they are the parent clocks for other clocks, in order to
use assigned-clock-parents in device tree, the ".fw_name" can't be used,
need to assign the clk_hw pointer for the imx8qm_mclk_sels[],
imx8qxp_mclk_sels[], imx8dxl_mclk_sels[].

Signed-off-by: Shengjiu Wang &lt;shengjiu.wang@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Link: https://lore.kernel.org/r/1720600860-18866-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
"acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM
driver, but they are the parent clocks for other clocks, in order to
use assigned-clock-parents in device tree, the ".fw_name" can't be used,
need to assign the clk_hw pointer for the imx8qm_mclk_sels[],
imx8qxp_mclk_sels[], imx8dxl_mclk_sels[].

Signed-off-by: Shengjiu Wang &lt;shengjiu.wang@nxp.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Link: https://lore.kernel.org/r/1720600860-18866-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx: composite-7ulp: Use NULL instead of 0</title>
<updated>2024-06-24T11:22:08+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2024-06-24T02:43:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=466da3d2d967ee87d82060df2bc9c6ad4fc4af49'/>
<id>466da3d2d967ee87d82060df2bc9c6ad4fc4af49</id>
<content type='text'>
Address the sparse warnings "
sparse warnings: (new ones prefixed by &gt;&gt;)
&gt;&gt; drivers/clk/imx/clk-composite-7ulp.c:85:24: sparse: sparse:
Using plain integer as NULL pointer
"

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Closes: https://lore.kernel.org/oe-kbuild-all/202406220536.JnAncjqz-lkp@intel.com/
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240624024351.488492-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Address the sparse warnings "
sparse warnings: (new ones prefixed by &gt;&gt;)
&gt;&gt; drivers/clk/imx/clk-composite-7ulp.c:85:24: sparse: sparse:
Using plain integer as NULL pointer
"

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Closes: https://lore.kernel.org/oe-kbuild-all/202406220536.JnAncjqz-lkp@intel.com/
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240624024351.488492-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx: add missing MODULE_DESCRIPTION() macros</title>
<updated>2024-06-24T11:21:09+00:00</updated>
<author>
<name>Jeff Johnson</name>
<email>quic_jjohnson@quicinc.com</email>
</author>
<published>2024-06-02T15:59:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1919d77a9591aa692c8de11540ffc0e7d18eabb4'/>
<id>1919d77a9591aa692c8de11540ffc0e7d18eabb4</id>
<content type='text'>
make allmodconfig &amp;&amp; make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/mxc-clk.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/clk-imxrt1050.o

Add the missing invocations of the MODULE_DESCRIPTION() macro.

Signed-off-by: Jeff Johnson &lt;quic_jjohnson@quicinc.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240602-md-clk-imx-v1-1-5c6d240f6fab@quicinc.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
make allmodconfig &amp;&amp; make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/mxc-clk.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/clk-imxrt1050.o

Add the missing invocations of the MODULE_DESCRIPTION() macro.

Signed-off-by: Jeff Johnson &lt;quic_jjohnson@quicinc.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240602-md-clk-imx-v1-1-5c6d240f6fab@quicinc.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate</title>
<updated>2024-06-21T06:35:30+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2024-05-31T20:26:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=ff06ea04e4cf3ba2f025024776e83bfbdfa05155'/>
<id>ff06ea04e4cf3ba2f025024776e83bfbdfa05155</id>
<content type='text'>
The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These
clocks are usually the only downstream clock from Video PLL on i.MX8MP.
Allow these clocks to reconfigure the Video PLL, as that results in
accurate pixel clock. If the Video PLL is not reconfigured, the pixel
clock accuracy is low.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240531202648.277078-1-marex@denx.de
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These
clocks are usually the only downstream clock from Video PLL on i.MX8MP.
Allow these clocks to reconfigure the Video PLL, as that results in
accurate pixel clock. If the Video PLL is not reconfigured, the pixel
clock accuracy is low.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240531202648.277078-1-marex@denx.de
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx: fracn-gppll: update rate table</title>
<updated>2024-06-21T06:35:30+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2024-06-07T13:33:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2c3499c761e0d695f08463943c1bca95ffc92d68'/>
<id>2c3499c761e0d695f08463943c1bca95ffc92d68</id>
<content type='text'>
- Add 1039.5MHz clock for video PLL to fulfill the LVDS display
  148.5MHz * 7 requirement
- Add 800MHz clock for ARM PLL

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240607133347.3291040-16-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- Add 1039.5MHz clock for video PLL to fulfill the LVDS display
  148.5MHz * 7 requirement
- Add 800MHz clock for ARM PLL

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240607133347.3291040-16-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: imx: imx8qxp: Parent should be initialized earlier than the clock</title>
<updated>2024-06-21T06:35:29+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2024-06-07T13:33:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=766c386c16c9899461b83573a06380d364c6e261'/>
<id>766c386c16c9899461b83573a06380d364c6e261</id>
<content type='text'>
The initialization order of SCU clocks affects the sequence of SCU clock
resume. If there are no other effects, the earlier the initialization,
the earlier the resume. During SCU clock resume, the clock rate is
restored. As SCFW guidelines, configure the parent clock rate before
configuring the child rate.

Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks")
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240607133347.3291040-15-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The initialization order of SCU clocks affects the sequence of SCU clock
resume. If there are no other effects, the earlier the initialization,
the earlier the resume. During SCU clock resume, the clock rate is
restored. As SCFW guidelines, configure the parent clock rate before
configuring the child rate.

Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks")
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Link: https://lore.kernel.org/r/20240607133347.3291040-15-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
