linux-toradex.git/drivers/clk/ingenic, branch v5.15-rc2

clk: ingenic: Add support for the JZ4760

2021-06-28T02:49:18+00:00

Add the CGU code and the compatible string to the TCU driver to support
the JZ4760 SoC.

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.net
Signed-off-by: Stephen Boyd

clk: ingenic: Support overriding PLLs M/N/OD calc algorithm

2021-06-28T02:49:18+00:00

SoC-specific code can now provide a callback if they need to compute the
M/N/OD values in a specific way.

Signed-off-by: Paul Cercueil 
Tested-by: 周琰杰 (Zhou Yanjie)   # on CU1000-neo/X1000E
Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net
Signed-off-by: Stephen Boyd

clk: ingenic: Remove pll_info.no_bypass_bit

2021-06-28T02:49:17+00:00

We can express that a PLL has no bypass bit by simply setting the
.bypass_bit field to a negative value.

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net
Tested-by: 周琰杰 (Zhou Yanjie) # on CU1830-neo/X1830
Signed-off-by: Stephen Boyd

clk: ingenic: Read bypass register only when there is one

2021-06-28T02:49:17+00:00

Rework the clock code so that the bypass register is only read when
there is actually a bypass functionality.

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net
Tested-by: 周琰杰 (Zhou Yanjie) # on CU1830-neo/X1830
Signed-off-by: Stephen Boyd

clk: Support bypassing dividers

2021-06-28T02:49:17+00:00

When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU
code expects the mux to be applied first, the divider second.

On the JZ4760, and maybe on some other SoCs, some clocks also have a mux
setting and a divider, but the divider is not applied to all parents
selectable from the mux.

This could be solved by creating two clocks, one with CGU_CLK_DIV and
one with CGU_CLK_MUX, but that would increase the number of clocks.

Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit
corresponding to the parent clock's index is set, the divider is
bypassed.

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd

clk: ingenic: Fix divider calculation with div tables

2020-12-20T00:04:58+00:00

The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.

Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.

Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables")
Cc:  # 5.2
Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd

clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate

2020-10-14T03:04:50+00:00

Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
should modify the value pointed to by parent_rate, in order to propagate
the rate change to the parent, as explained in the documentation of
clk_set_rate().

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net
Signed-off-by: Stephen Boyd

clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT

2020-10-14T03:04:50+00:00

The custom clocks have custom functions to round, get or set their rate.
Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net
Signed-off-by: Stephen Boyd

clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

2020-10-14T03:04:50+00:00

CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd

clk: ingenic: Use readl_poll_timeout instead of custom loop

2020-10-14T03:04:50+00:00

Use the readl_poll_timeout() function instead of rolling our own
busy-wait loops. This makes the code simpler.

Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net
Signed-off-by: Stephen Boyd