linux-toradex.git/drivers/clk/mediatek/clk-mt6795-topckgen.c, branch master

clk: Switch back to struct platform_driver::remove()

2024-09-21T21:12:05+00:00

After commit 0edb555a65d1 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.

Convert all clk drivers to use .remove(), with the eventual goal to drop
struct platform_driver::remove_new(). As .remove() and .remove_new() have
the same prototypes, conversion is done by just changing the structure
member name in the driver initializer.

Signed-off-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com
Acked-by: Geert Uytterhoeven  # renesas
Signed-off-by: Stephen Boyd

clk: mediatek: Make mtk_clk_simple_remove() return void

2023-05-10T20:36:03+00:00

__mtk_clk_simple_remove() and so also mtk_clk_simple_remove() return
zero unconditionally. Make them return no value instead and convert the
drivers making use of it to platform_driver's .remove_new().

This makes the semantics in the callers of mtk_clk_simple_remove() clearer
and prepares for the quest to make platform driver's remove function return
void. There is no semantic change.

Signed-off-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/20230430190233.878921-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd

clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriate

2023-03-13T18:50:18+00:00

Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules
to allow auto-load at boot.

Signed-off-by: AngeloGioacchino Del Regno 
Reviewed-by: Chen-Yu Tsai 
Tested-by: Miles Chen 
Tested-by: Chen-Yu Tsai  # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd

clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe()

2023-01-31T00:45:57+00:00

Migrate away from custom probe functions and use the commonized
mtk_clk_simple_{probe, remove}().

Signed-off-by: AngeloGioacchino Del Regno 
Reviewed-by: Miles Chen 
Reviewed-by: Chen-Yu Tsai 
Link: https://lore.kernel.org/r/20230120092053.182923-22-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su 
Signed-off-by: Stephen Boyd

clk: mediatek: clk-mux: Propagate struct device for mtk-mux

2023-01-31T00:45:10+00:00

Like done for other clocks, propagate struct device for mtk mux clocks
registered through clk-mux helpers to enable runtime pm support.

Signed-off-by: AngeloGioacchino Del Regno 
Tested-by: Miles Chen 
Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su 
Signed-off-by: Stephen Boyd

clk: mediatek: clk-mtk: Propagate struct device for composites

2023-01-31T00:45:06+00:00

Like done for cpumux clocks, propagate struct device for composite
clocks registered through clk-mtk helpers to be able to get runtime
pm support for MTK clocks.

Signed-off-by: AngeloGioacchino Del Regno 
Tested-by: Miles Chen 
Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su 
Signed-off-by: Stephen Boyd

clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factors

2022-11-29T06:42:41+00:00

The main/sys/univpll clocks are used as clock sources for multiple
peripherals of different kind, some of which are critical (like AXIs);
a rate change on any of these two will produce a rate change on many
devices and that's likely to produce system instability if not done
correctly: this is the reason why we have (a lot of) "fixed factor"
main/sys/univpll divider clocks, used by MUX clocks to provide
different rates based on PLL output dividers.

Following what was done on clk-mt8186-topckgen and also preventing the
same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned
clocks.

Signed-off-by: AngeloGioacchino Del Regno 
Reviewed-by: Chen-Yu Tsai 
Link: https://lore.kernel.org/r/20221024102307.33722-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai

clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers

2022-09-26T03:13:09+00:00

Add the clock drivers for the entire clock tree of MediaTek Helio X10
MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen)
and multimedia clocks (mmsys, mfg, vdecsys, vencsys).

Signed-off-by: AngeloGioacchino Del Regno 
Reviewed-by: Matthias Brugger 
Reviewed-by: Miles Chen 
Link: https://lore.kernel.org/r/20220921091455.41327-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai