linux-toradex.git/drivers/clk/mediatek, branch v4.9.97

clk: mediatek: add the option for determining PLL source clock

2017-12-20T09:07:29+00:00

[ Upstream commit c955bf3998efa3355790a4d8c82874582f1bc727 ]

Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: Chen Zhong 
Signed-off-by: Sean Wang 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: mediatek: Add hardware dependency

2016-10-17T22:22:26+00:00

Only propose the mediatek clock drivers on this platform, unless
build-testing.

Signed-off-by: Jean Delvare 
Cc: Shunli Wang 
Cc: James Liao 
Cc: Erin Lo 
Cc: Matthias Brugger 
Cc: Michael Turquette 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd

clk: mediatek: clk-mt8173: Unmap region obtained by of_iomap

2016-09-21T08:06:07+00:00

Free memory mapping if init is not successful.

Signed-off-by: Arvind Yadav 
Reviewed-by: James Liao 
Signed-off-by: Stephen Boyd

clk: mediatek: Refine the makefile to support multiple clock drivers

2016-08-19T19:18:38+00:00

Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Signed-off-by: Erin Lo 
Tested-by: John Crispin 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd

clk: mediatek: remove __init from clk registration functions

2016-08-19T00:15:30+00:00

Remove __init from functions that will be used by init functions
that support probe deferral.

Signed-off-by: James Liao 
Signed-off-by: Erin Lo 
Signed-off-by: Stephen Boyd

clk: mediatek: remove hdmitx_dig_cts from TOP clocks

2016-05-06T15:47:42+00:00

The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.

Signed-off-by: Philipp Zabel 
Acked-by: Stephen Boyd

clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output

2016-05-06T15:47:40+00:00

The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel 
Acked-by: James Liao 
Acked-by: Stephen Boyd

clk: mediatek: make dpi0_sel propagate rate changes

2016-05-06T15:47:39+00:00

This mux is supposed to select a fitting divider after the PLL
is already set to the correct rate.

Signed-off-by: Philipp Zabel 
Acked-by: James Liao 
Acked-by: Stephen Boyd

clk: mediatek: Make reset_control_ops const

2016-03-29T23:29:19+00:00

The mtk_reset_ops structure is never modified. Make it const.

Signed-off-by: Philipp Zabel 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd

clk: mediatek: Remove CLK_IS_ROOT

2016-03-03T01:44:06+00:00

This flag is a no-op now. Remove usage of the flag.

Acked-by: James Liao 
Signed-off-by: Stephen Boyd