These > comparisons should be >= to prevent reading beyond the end of
of the clk_data->hws[] buffer.
The clk_data->hws[] array is allocated in cp110_syscon_common_probe()
when we do:
cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) +
sizeof(struct clk_hw *) * CP110_CLK_NUM,
GFP_KERNEL);
As you can see, it has CP110_CLK_NUM elements which is equivalent to
CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS.
Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system controller")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pull clk updates from Stephen Boyd: "This time it looks like a quieter release cycle in the clk tree. I guess that's because of summer time holidays/vacations. The biggest change in the diffstat is in the Qualcomm clk driver, where they got support for CPUs and handful of SoCs. After that, the at91 driver got a major rewrite for newer DT bindings that should make things easier going forward and the TI code moved to a clockdomain based design. The long tail is mostly small driver updates for newer clks and some simpler SoC clock drivers such as the Hisilicon and imx support. In the core framework, we only have two small changes this time. One is a new clk API to get all clks for a device with the bulk clk APIs. This allows drivers that don't care about doing anything besides turning on all the clks to just clk_get() them all and turn them on. The other change is the beginning of a way to support save and restore of clk settings in the clk framework. TI is the only user right now, but we will want to expand upon this design in the future to support more save and restore of clk registers. At least this gets us started and works well enough for one SoC, but there's more work in the future. Core: - clk_bulk_get_all() API and friends to get all the clks for a device - Basic clk state save/restore hooks New Drivers: - Renesas RZ/A2 (R7S9210) SoC, including early clocks - Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs - Rensas RZ/G2M (r8a774a1) SoC - Qualcomm Krait CPU clk support - Qualcomm QCS404 GCC support - Qualcomm SDM660 GCC support - Qualcomm SDM845 camera clock controller - Ingenic jz4725b CGU - Hisilicon 3670 SoC support - TI SCI clks on K3 SoCs - iMX6 MMDC clks - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs Updates: - Rework at91 PMC clock driver for new DT bindings - Nvidia Tegra clk driver MBIST workaround fix - S2RAM support for Marvell mvebu periph clks - Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 - Add support for CMT timer clocks on R-Car V3H - Add support for SHDI and various timer clocks on R-Car V3M - Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs - Amlogic clk-pll driver improvements and updates - Amlogic axg audio controller system clocks - Register Amlogic meson8b clock controller early - Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N - Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers - Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC - Remove obsoleted Exynos4212 ISP clock definitions - Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design - TI RTC+DDR sleep mode support for clock save/restore - Allwinner A64 display engine support and fixes - Allwinner A83t display engine support and fixes" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (186 commits) clk: qcom: Remove unused arrays in SDM845 GCC clk: fixed-rate: fix of_node_get-put imbalance clk: s2mps11: Add used attribute to s2mps11_dt_match clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock ...
- S2RAM support for Marvell mvebu periph clks * clk-mvebu-periph-pm: clk: mvebu: armada-37xx-periph: add suspend/resume support clk: mvebu: armada-37xx-periph: save the IP base address in the driver data * clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit * clk-allwinner: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position * clk-mvebu-dup: clk: mvebu: ap806: Remove superfluous of_clk_add_provider * clk-davinci: clk: davinci: kill davinci_clk_reset_assert/deassert()
- Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds * clk-dt-name: clk: Convert to using %pOFn instead of device_node.name * clk-ti-of-node: clk: ti: fix OF child-node lookup * clk-sa: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe reset: hisilicon: fix potential NULL pointer dereference clk: cdce925: release child device nodes clk: qcom: clk-branch: Use true and false for boolean values
The parent clock is get only to have its name, and then the clock is no more used, so we can safely free it using clk_put. Furthermore as between the successful devm_clk_get() and the devm_clk_put() call we don't exit the probe function in error so I can use non managed version of clk_get() and clk_put(). Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
While applying the commit a8309cedcdce ("clk: apn806: Add eMMC clock to
system controller driver"), of_clk_add_provider was added wheres it was
already present in the probe function.
This extraneous call is harmless but not useful so remove it.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the remaining files to SPDX license description. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use the for_each_of_cpu_node iterator to iterate over cpu nodes. This has the side effect of defaulting to iterating using "cpu" node names in preference to the deprecated (for FDT) device_type == "cpu". Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
Add suspend/resume hooks in Armada 37xx peripheral clocks driver to handle S2RAM operations. One can think that these hooks are useless by comparing the register values before and after a suspend/resume cycle: they will look the same anyway. This is because of some scripts executed by the Cortex-M3 core during ATF operations to init both the clocks and the DDR. These values could be modified by the BL33 stage or by Linux itself and should be preserved. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Prepare the introduction of suspend/resume hooks by having an easy way to access all the registers in one go just from a device: add the IP base address in the driver data. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>