linux-toradex.git/drivers/clk/pistachio, branch v4.1.21

clk: pistachio: correct critical clock list

2015-09-21T17:05:31+00:00

commit d31ff5f7f3b142b8d1ebb3da89187c54cdf2bc71 upstream.

Current critical clock list for pistachio enables
only mips and sys clocks by default but there are
also other clocks that are not claimed by anyone and
needs to be enabled by default.

This patch updates the critical clocks that need
to be enabled by default.

Add a separate struct to distinguish the critical clocks
as listed:
1.) core clocks:
	a.) mips clock
2.) peripheral system clocks:
	a.) sys clock
	b.) sys_bus clock
	c.) DDR clock
	d.) ROM clock

Fixes: b35d7c33419c("CLK: Pistachio: Register core clocks")
Reviewed-by: Andrew Bresticker 
Signed-off-by: Ezequiel Garcia 
Signed-off-by: Damien.Horsley 
Signed-off-by: Govindraj Raja 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: pistachio: Fix override of clk-pll settings from boot loader

2015-09-21T17:05:31+00:00

commit e53f21c761d141bbcbce06e9ddab3b4e0a828f2c upstream.

PLL enable callbacks are overriding PLL mode (int/frac) and
Noise reduction (on/off) settings set by the boot loader which
results in the incorrect clock rate.

PLL mode and noise reduction are defined by the DSMPD and DACPD bits
of the PLL control register. PLL .enable() callbacks enable PLL
by deasserting all power-down bits of the PLL control register,
including DSMPD and DACPD bits, which is not necessary since
these bits don't actually enable/disable PLL.

This commit fixes the problem by removing DSMPD and DACPD bits
from the "PLL enable" mask.

Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Reviewed-by: Andrew Bresitcker 
Signed-off-by: Zdenko Pulitika 
Signed-off-by: Govindraj Raja 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

CLK: Pistachio: Register external clock gates

2015-03-31T09:59:31+00:00

Register the clock gates for the external audio and ethernet
reference clocks provided by the top-level general control block.

Signed-off-by: Damien Horsley 
Signed-off-by: Andrew Bresticker 
Cc: Mike Turquette 
Cc: Stephen Boyd 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia 
Cc: James Hartley 
Cc: James Hogan 
Acked-by: Stephen Boyd 
Patchwork: https://patchwork.linux-mips.org/patch/9321/
Signed-off-by: Ralf Baechle

CLK: Pistachio: Register system interface gate clocks

2015-03-31T09:59:24+00:00

Register the system interface gate clocks provided by the peripheral
general control block.  These clocks gate register access for various
peripherals.

Signed-off-by: Damien Horsley 
Signed-off-by: Andrew Bresticker 
Cc: Mike Turquette 
Cc: Stephen Boyd 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia 
Cc: James Hartley 
Cc: James Hogan 
Acked-by: Stephen Boyd 
Patchwork: https://patchwork.linux-mips.org/patch/9322/
Signed-off-by: Ralf Baechle

CLK: Pistachio: Register peripheral clocks

2015-03-31T09:59:17+00:00

Register the clocks generated by the peripheral clock controller.
This includes the clocks for several peripherals, including I2C,
PWM, watchdog, and timer.

Signed-off-by: Damien Horsley 
Signed-off-by: Andrew Bresticker 
Cc: Mike Turquette 
Cc: Stephen Boyd 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia 
Cc: James Hartley 
Cc: James Hogan 
Acked-by: Stephen Boyd 
Patchwork: https://patchwork.linux-mips.org/patch/9320/
Signed-off-by: Ralf Baechle

CLK: Pistachio: Register core clocks

2015-03-31T09:59:10+00:00

Register the clocks generated by the core clock controller.
This includes the 7 PLLs and clocks for the CPU, RPU co-processor,
audio, WiFi, bluetooth, and several other peripherals.

The MIPS and PERIPH_SYS clocks must remain enabled at all times.

Signed-off-by: Damien Horsley 
Signed-off-by: Andrew Bresticker 
Cc: Mike Turquette 
Cc: Stephen Boyd 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia 
Cc: James Hartley 
Cc: James Hogan 
Acked-by: Stephen Boyd 
Patchwork: https://patchwork.linux-mips.org/patch/9317/
Signed-off-by: Ralf Baechle

CLK: Pistachio: Add PLL driver

2015-03-31T09:59:04+00:00

Add a driver for the integer (GF40LP_LAINT) and fractional (GF40LP_FRAC)
PLLs present on Pistachio.

Signed-off-by: Andrew Bresticker 
Cc: Mike Turquette 
Cc: Stephen Boyd 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia 
Cc: James Hartley 
Cc: James Hogan 
Acked-by: Stephen Boyd 
Patchwork: https://patchwork.linux-mips.org/patch/9316/
Signed-off-by: Ralf Baechle

CLK: Add basic infrastructure for Pistachio clocks

2015-03-31T09:58:56+00:00

Add helpers for registering clocks and clock providers on Pistachio.

Signed-off-by: Andrew Bresticker 
Cc: Mike Turquette 
Cc: Stephen Boyd 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia 
Cc: James Hartley 
Cc: James Hogan 
Acked-by: Stephen Boyd 
Patchwork: https://patchwork.linux-mips.org/patch/9318/
Signed-off-by: Ralf Baechle