linux-toradex.git/drivers/clk/qcom, branch v3.14.57

clk: qcom: fix RCG M/N counter configuration

2015-05-06T19:59:18+00:00

commit 0b21503dbbfa669dbd847b33578d4041513cddb2 upstream.

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja 
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: mdp_lut_clk is a child of mdp_src

2014-10-05T21:52:24+00:00

commit f87dfcabc6f173cc811d185d33327f50a8c88399 upstream.

The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the
child of the mdp_src clock. Fix it.

Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix MN frequency tables, parent map, and jpegd

2014-10-05T21:52:24+00:00

commit ff20783f7b9f35b29e768d8ecc7076c1ca1a60ca upstream.

Clocks that don't have a pre-divider don't list any pre-divider
in their frequency tables, but their tables are initialized using
aggregate initializers. Use tagged initializers so we properly
assign the m and n values for each frequency. Furthermore, the
mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second
element to pll2 instead of pll8, causing the clock driver to
recalculate the wrong rate for any clocks using this array along
with a rate that uses pll2. Plus the .num_parents field is 3
instead of 4 so you can't even switch the parent to pll3. Finally
I noticed that the jpegd clock improperly indicates that the
pre-divider width is only 2, when it's actually 4 bits wide.

Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Tested-by: Rob Clark 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: HDMI source sel is 3 not 2

2014-07-17T23:21:05+00:00

commit c556bcddc78096caeb46dbe3ad0314dd951f1665 upstream.

The HDMI PLL input to the tv mux is supposed to be 3, not 2. Fix
the code so that we can properly select the HDMI PLL.

Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Reported-by: Rob Clark 
Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix mmcc-8974's PLL configurations

2014-07-09T18:18:28+00:00

commit 437ae6a1b8f2eedebfbf0f6572e19ca5c58a3f71 upstream.

We forgot to add the status bit for the PLLs and we were using
the wrong register and masks for configuration, leading to
unexpected PLL configurations. Fix this.

Fixes: d8b212014e69 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC))
Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix clk_rcg2_is_enabled() check

2014-07-09T18:18:28+00:00

commit aa014149ba002155a084ec1e9328e95b70167cbb upstream.

If the bit is set the clock is off so we should be checking for
a clear bit, not a set bit. Invert the logic.

Fixes: bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs))
Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix modular build

2014-01-17T21:39:42+00:00

According to Documentation/kbuild/makefiles.txt these symbols
should be clk-qcom-y. Otherwise the build will fail if
CONFIG_COMMON_CLK_QCOM=m. Fix it.

Reported-by: kbuild test robot 
Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette

clk: qcom: Add support for MSM8660's global clock controller (GCC)

2014-01-16T20:01:05+00:00

Add a driver for the global clock controller found on MSM8660
based platforms. This should allow most non-multimedia device
drivers to probe and control their clocks.

Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette

clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)

2014-01-16T20:01:05+00:00

Add a driver for the global clock controller found on MSM 8974
based platforms. This should allow most multimedia device drivers
to probe and control their clocks.

Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette

clk: qcom: Add support for MSM8974's global clock controller (GCC)

2014-01-16T20:01:04+00:00

Add a driver for the global clock controller found on MSM 8974
based platforms. This should allow most non-multimedia device
drivers to probe and control their clocks.

Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette