linux-toradex.git/drivers/clk/qcom, branch v4.5

Revert "clk: qcom: Specify LE device endianness"

2016-02-12T22:24:24+00:00

This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87.

The commit that caused us to specify LE device endianness here,
29bb45f25ff3 (regmap-mmio: Use native endianness for read/write,
2015-10-29), has been reverted in mainline so now when we specify
LE it actively breaks big endian kernels because the byte
swapping in regmap-mmio is incorrect. Let's revert this change
because it will 1) fix the big endian kernels and 2) be redundant
to specify LE because that will become the default soon.

Cc: Kevin Hilman 
Tested-by: Kevin Hilman 
Cc: Mark Brown 
Signed-off-by: Stephen Boyd

Merge branch 'clk-msm8996' into clk-next

2015-12-01T08:00:48+00:00

* clk-msm8996:
  clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver
  clk: qcom: Add gfx3d ping-pong PLL frequency switching
  clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
  clk: qcom: Add Alpha PLL support
  clk: divider: Cap table divider values to 'width' member

clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver

2015-12-01T02:24:30+00:00

Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.

Signed-off-by: Stephen Boyd

clk: qcom: Add gfx3d ping-pong PLL frequency switching

2015-12-01T02:24:29+00:00

The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2,
MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624
MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To
make switching frequencies faster, we ping-pong between MMPLL2
and MMPLL8 when we're switching between frequencies that aren't
the maximum. Implement custom rcg clk ops for this type of
frequency switching.

Signed-off-by: Stephen Boyd

clk: qcom: Add MSM8996 Global Clock Control (GCC) driver

2015-12-01T02:24:27+00:00

Add support for the global clock controller found on MSM8996
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.

Signed-off-by: Stephen Boyd

clk: qcom: Add Alpha PLL support

2015-12-01T02:24:25+00:00

Add support for configuring rates of, enabling, and disabling
Alpha PLLs. This is sufficient for the types of PLLs found in
the global and multimedia clock controllers.

Signed-off-by: Stephen Boyd

clk: qcom: msm8916: Move xo and sleep clocks into DT

2015-11-21T00:40:47+00:00

Move the xo and sleep clocks to device-tree, instead of hard-coding
them in the driver. This allows us to insert the RPM clocks (if they
are enabled) in between the on-board oscillators and the actual clock.

Signed-off-by: Georgi Djakov 
Signed-off-by: Stephen Boyd

clk: qcom: Specify LE device endianness

2015-11-20T21:14:43+00:00

All these clock controllers are little endian devices, but so far
we've been relying on the regmap mmio bus handling this for us
without explicitly stating that fact. After commit 4a98da2164cf
(regmap-mmio: Use native endianness for read/write, 2015-10-29),
the regmap mmio bus will read/write with the __raw_*() IO
accessors, instead of using the readl/writel() APIs that do
proper byte swapping for little endian devices.

So if we're running on a big endian processor and haven't
specified the endianness explicitly in the regmap config or in
DT, we're going to switch from doing little endian byte swapping
to big endian accesses without byte swapping, leading to some
confusing results. On my apq8074 dragonboard, this causes the
device to fail to boot as we access the clock controller with
big endian IO accesses even though the device is little endian.

Specify the endianness explicitly so that the regmap core
properly byte swaps the accesses for us.

Reported-by: Kevin Hilman 
Tested-by: Tyler Baker 
Tested-by: Kevin Hilman 
Cc: Simon Arlott 
Cc: Mark Brown 
Signed-off-by: Stephen Boyd

clk: qcom: Move cxo/pxo/xo into dt files

2015-11-16T19:07:06+00:00

Put these clocks into the dt files instead of registering them
from C code. This provides a few benefits. It allows us to
specify the frequency of these clocks at the board level instead
of hard-coding them in the driver. It allows us to insert an RPM
clock in between the consumers of the crystals and the actual
clock. And finally, it helps us transition the GCC driver to use
RPM clocks when that configuration is enabled.

Cc: Georgi Djakov 
Signed-off-by: Stephen Boyd

clk: qcom: common: Add API to register board clocks backwards compatibly

2015-11-16T19:07:06+00:00

We want to put the XO board clocks into the dt files, but we also
need to be backwards compatible with an older dtb. Add an API to
the common code to do this. This also makes a place for us to
handle the case when the RPM clock driver is enabled and we don't
want to register the fixed factor clock.

Cc: Georgi Djakov 
Signed-off-by: Stephen Boyd