linux-toradex.git/drivers/clk/qcom, branch v5.19

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2022-05-27T22:33:24+00:00

Pull clk updates from Stephen Boyd:
 "Mainly driver updates this time around.

  There's a single patch to the core clk framework that simplifies a
  runtime PM call. Otherwise the majority of the diff falls to a few SoC
  drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some new
  hardware support and what comes along with that is quite a few lines
  of data and some clk_ops code.

  Beyond the new hardware support we have the usual pile of driver
  updates that add missing clks on already supported SoCs or fix up
  problems like bad clk tree descriptions. It's nice to see that more
  drivers are moving to clk_hw based APIs too.

  New Drivers:
   - Add STM32MP13 RCC driver (Reset Clock Controller)
   - MediaTek MT8186 SoC clk support
   - Airoha EN7523 SoC system clocks
   - Clock driver for exynosautov9 SoC
   - Renesas R-Car V4H and RZ/V2M SoCs
   - Renesas RZ/G2UL SoC
   - LPASS clk driver for Qualcomm sc7280 SoC
   - GCC clk driver for Qualcomm SC8280XP SoC

  Updates:
   - SDCC uses floor clk ops on Qualcomm MSM8976
   - Add modem reset and fix RPM clks on Qualcomm MSM8976
   - Add the two missing CLKOUT clocks for U8500/DB8500 SoC
   - Mark some clks critical on Ingenic X1000
   - Convert ux500 to clk_hw
   - Move MediaTek driver to clk_hw provider APIs
   - Use i2c driver probe_new to avoid id scans
   - Convert a number of Rockchip dt bindings to YAML
   - Mark hclk_vo critical on Rockchip rk3568
   - Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
   - Various cleanups like memory allocation error checks and plugged
     leaks
   - Allwinner H6 RTC clock support
   - Allwinner H616 32 kHz clock support
   - Add the Universal Flash Storage clock on Renesas R-Car S4-8
   - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
     I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas
     RZ/G2UL
   - Add display clock support on Renesas RZ/G2L
   - Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
   - Add 27 MHz phy PLL ref clock on i.MX
   - Add mcore_booted module parameter to tell kernel M core has already
     booted for i.MX
   - Remove snvs clock on i.MX because it was for secure world only
   - Add dt bindings for i.MX8MN GPT
   - Add DISP2 pixel clock for i.MX8MP
   - Add clkout1/2 for i.MX8MP
   - Fix parent clock of ubs_root_clk for i.MX8MP
   - Implement better RCG parking on Qualcomm SoCs using the shared RCG
     clk ops
   - Kerneldoc fixes
   - Switch Tegra BPMP to determine_rate clk op
   - Add a pointer to dt schema for generic clock bindings"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (168 commits)
  Revert "clk: qcom: regmap-mux: add pipe clk implementation"
  Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
  Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
  clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
  clk: stm32mp13: add safe mux management
  clk: stm32mp13: add multi mux function
  clk: stm32mp13: add all STM32MP13 kernel clocks
  clk: stm32mp13: add all STM32MP13 peripheral clocks
  clk: stm32mp13: manage secured clocks
  clk: stm32mp13: add composite clock
  clk: stm32mp13: add stm32 divider clock
  clk: stm32mp13: add stm32_gate management
  clk: stm32mp13: add stm32_mux clock management
  clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
  dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
  clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
  clk: ti: composite: Prefer kcalloc over open coded arithmetic
  dt-bindings: clock: exynosautov9: correct count of NR_CLK
  clk: mediatek: mt8173: Switch to clk_hw provider APIs
  clk: mediatek: Switch to clk_hw provider APIs
  ...

Revert "clk: qcom: regmap-mux: add pipe clk implementation"

2022-05-23T17:26:13+00:00

Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Pipe clocks
has been updated to use newer and simpler clk_regmap_phy_mux_ops. Drop
the regmap-mux-safe clock ops now.

Signed-off-by: Dmitry Baryshkov 
Reviewed-by: Johan Hovold 
Tested-by: Reviewed-by: Johan Hovold 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220521005343.1429642-4-dmitry.baryshkov@linaro.org

Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"

2022-05-23T17:26:13+00:00

Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Revert the
commit that switches gcc-sc7280 driver to use regmap_mux_safe.

Signed-off-by: Dmitry Baryshkov 
Reviewed-by: Johan Hovold 
Tested-by: Reviewed-by: Johan Hovold 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220521005343.1429642-3-dmitry.baryshkov@linaro.org

Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"

2022-05-23T17:26:13+00:00

Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Revert the
commit that switches gcc-sm8450 driver to use regmap_mux_safe.

Signed-off-by: Dmitry Baryshkov 
Reviewed-by: Johan Hovold 
Tested-by: Reviewed-by: Johan Hovold 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220521005343.1429642-2-dmitry.baryshkov@linaro.org

clk: qcom: rcg2: Cache CFG register updates for parked RCGs

2022-05-19T21:42:30+00:00

As GDSCs are turned on and off some associated clocks are momentarily
enabled for house keeping purposes. For this, and similar, purposes the
"shared RCGs" will park the RCG on a source clock which is known to be
available.
When the RCG is parked, a safe clock source will be selected and
committed, then the original source would be written back and upon enable
the change back to the unparked source would be committed.

But starting with SM8350 this fails, as the value in CFG is committed by
the GDSC handshake and without a ticking parent the GDSC enablement will
time out.

This becomes a concrete problem if the runtime supended state of a
device includes disabling such rcg's parent clock. As the device
attempts to power up the domain again the rcg will fail to enable and
hence the GDSC enablement will fail, preventing the device from
returning from the suspended state.

This can be seen in e.g. the display stack during probe on SM8350.

To avoid this problem, the software needs to ensure that the RCG is
configured to a active parent clock while it is disabled. This is done
by caching the CFG register content while the shared RCG is parked on
this safe source.

Writes to M, N and D registers are committed as they are requested. New
helpers for get_parent() and recalc_rate() are extracted from their
previous implementations and __clk_rcg2_configure() is modified to allow
it to operate on the cached value.

Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed")
Signed-off-by: Bjorn Andersson 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20220426212136.1543984-1-bjorn.andersson@linaro.org

clk: qcom: add sc8280xp GCC driver

2022-05-19T21:41:32+00:00

Add support for the Global Clock Controller found in the Qualcomm
SC8280XP platform.

Signed-off-by: Bjorn Andersson 
Reviewed-by: Vinod Koul 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org

clk: qcom: gcc-msm8976: Add modem reset

2022-05-06T03:22:27+00:00

Add modem reset, it will be needed during modem bringup.

Signed-off-by: Adam Skladowski 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220426073048.11509-4-a39.skl@gmail.com

clk: qcom: gcc-msm8976: Set floor ops for SDCC

2022-05-06T03:22:27+00:00

Just like in case of other SoCs change SDCC1/SDCC2 ops
to floor to avoid overclocking controller.
This commit only sets SDCC1/SDCC2 which are used for EMMC/SDCARD.
Leave SDCC3 because on this platform it's mostly used for WIFI/BT chips,
like on Sony Loire familly devices.

Signed-off-by: Adam Skladowski 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220426073048.11509-2-a39.skl@gmail.com

clk: qcom: smd: Update MSM8976 RPM clocks.

2022-04-29T02:42:21+00:00

MSM8976 does not have rpm clock named mmssnoc,
instead it's called sysmmnoc, drop define and reuse.
While we are at it add XO clock to list.

Fixes: 7d61e773c3ed ("clk: qcom: smd: Add support for MSM8976 rpm clocks")
Signed-off-by: Adam Skladowski 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220426090226.27293-1-a39.skl@gmail.com

clk: qcom: clk-rcg2: fix gfx3d frequency calculation

2022-04-22T02:49:19+00:00

Since the commit 948fb0969eae ("clk: Always clamp the rounded rate"),
the clk_core_determine_round_nolock() would clamp the requested rate
between min and max rates from the rate request. Normally these fields
would be filled by clk_core_get_boundaries() called from
clk_round_rate().

However clk_gfx3d_determine_rate() uses a manually crafted rate request,
which did not have these fields filled. Thus the requested frequency
would be clamped to 0, resulting in weird frequencies being requested
from the hardware.

Fix this by filling min_rate and max_rate to the values valid for the
respective PLLs (0 and ULONG_MAX).

Fixes: 948fb0969eae ("clk: Always clamp the rounded rate")
Signed-off-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20220419235447.1586192-1-dmitry.baryshkov@linaro.org
Reviewed-by: Bjorn Andersson 
Reported-by: Rob Clark 
Signed-off-by: Stephen Boyd