linux-toradex.git/drivers/clk/qcom, branch v6.19 Linux kernel for Apalis and Colibri modules clk: qcom: Mark camcc_sm7150_hws static 2025-11-30T20:04:10+00:00 Stephen Boyd sboyd@kernel.org 2025-11-30T20:02:31+00:00 1413717ad0c6d3887192b0119ad6420dbf0c26ae This isn't used outside this file. Mark it static. Fixes: 9f0532da4226 ("clk: qcom: Add Camera Clock Controller driver for SM7150") Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
This isn't used outside this file. Mark it static.

Fixes: 9f0532da4226 ("clk: qcom: Add Camera Clock Controller driver for SM7150")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: qcom: x1e80100-dispcc: Add USB4 router link resets 2025-11-18T22:11:37+00:00 Konrad Dybcio konrad.dybcio@oss.qualcomm.com 2025-11-18T17:33:12+00:00 3664282f3345fdfa6a154feb6ed6c3217a8b3b0d The router link clock branches also feature some reset logic, which is required to properly power sequence the hardware for DP tunneling over USB4. Describe these missing resets. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-topic-usb4_x1e_dispcc-v1-2-14c68d842c71@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
The router link clock branches also feature some reset logic, which is
required to properly power sequence the hardware for DP tunneling over
USB4.

Describe these missing resets.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-topic-usb4_x1e_dispcc-v1-2-14c68d842c71@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750 2025-11-18T22:11:36+00:00 Taniya Das taniya.das@oss.qualcomm.com 2025-11-18T07:17:09+00:00 a160860529b55c54dbd54137f86c818a53d07655 Add support for the video clock controller for video clients to be able to request for videocc clocks on SM8750 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-5-049882a70c9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Add support for the video clock controller for video clients to be able
to request for videocc clocks on SM8750 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-5-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: branch: Extend invert logic for branch2 mem clocks 2025-11-18T22:11:29+00:00 Taniya Das taniya.das@oss.qualcomm.com 2025-11-18T07:17:07+00:00 aa788d3b475652a3ebaca32ca714f02f8ece3393 Some clock branches require inverted logic for memory gating, where disabling the memory involves setting a bit and enabling it involves clearing the same bit. This behavior differs from the standard approach memory branch clocks ops where enabling typically sets the bit. The mem_enable_invert to allow conditional handling of these sequences of the inverted control logic for memory operations required on those memory clock branches. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-3-049882a70c9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Some clock branches require inverted logic for memory gating, where
disabling the memory involves setting a bit and enabling it involves
clearing the same bit. This behavior differs from the standard approach
memory branch clocks ops where enabling typically sets the bit.

The mem_enable_invert to allow conditional handling of these sequences
of the inverted control logic for memory operations required on those
memory clock branches.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-3-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch 2025-11-18T16:30:43+00:00 Taniya Das taniya.das@oss.qualcomm.com 2025-11-18T07:17:06+00:00 53a18958349a627ae5d6b1ea708289b6cf3d8b9d The ECPRI clock controller’s mem_ops clocks used the mem_enable_ack_mask directly for both setting and polling. Add the newly introduced 'mem_enable_mask' to the memory control branch clocks of ECPRI clock controller to align to the new mem_ops handling. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-2-049882a70c9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
The ECPRI clock controller’s mem_ops clocks used the mem_enable_ack_mask
directly for both setting and polling.
Add the newly introduced 'mem_enable_mask' to the memory control branch
clocks of ECPRI clock controller to align to the new mem_ops handling.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-2-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: clk_mem_branch: add enable mask and invert flags 2025-11-18T16:30:43+00:00 Taniya Das taniya.das@oss.qualcomm.com 2025-11-18T07:17:05+00:00 165d0b6dd248b939fb0d31a00687e6ef672b3b3c Introduce mem_enable_mask and mem_enable_invert in clk_mem_branch to describe memory gating implementations that use a separate mask and/or inverted enable logic. This documents hardware behavior in data instead of code and will be used by upcoming platform descriptions. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-1-049882a70c9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Introduce mem_enable_mask and mem_enable_invert in clk_mem_branch to
describe memory gating implementations that use a separate mask and/or
inverted enable logic. This documents hardware behavior in data instead
of code and will be used by upcoming platform descriptions.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-1-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: mmcc-sdm660: Add missing MDSS reset 2025-11-18T16:29:03+00:00 Alexey Minnekhanov alexeymin@postmarketos.org 2025-11-16T01:12:34+00:00 0a0ea5541d30c0fbb3dac975bd1983f299cd6948 Add offset for display subsystem reset in multimedia clock controller block, which is necessary to reset display when there is some configuration in display controller left by previous stock (Android) bootloader to provide continuous splash functionaluty. Before 6.17 power domains were turned off for long enough to clear registers, now this is not the case and a proper reset is needed to have functioning display. Fixes: 0e789b491ba0 ("pmdomain: core: Leave powered-on genpds on until sync_state") Cc: stable@vger.kernel.org # 6.17 Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251116-sdm660-mdss-reset-v2-2-6219bec0a97f@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Add offset for display subsystem reset in multimedia clock controller
block, which is necessary to reset display when there is some
configuration in display controller left by previous stock (Android)
bootloader to provide continuous splash functionaluty.

Before 6.17 power domains were turned off for long enough to clear
registers, now this is not the case and a proper reset is needed to
have functioning display.

Fixes: 0e789b491ba0 ("pmdomain: core: Leave powered-on genpds on until sync_state")
Cc: stable@vger.kernel.org # 6.17
Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251116-sdm660-mdss-reset-v2-2-6219bec0a97f@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: use different Kconfig prompts for APSS IPQ5424/6018 drivers 2025-11-13T17:42:48+00:00 Gabor Juhos j4g8y7@gmail.com 2025-11-13T16:42:52+00:00 4145fc363eb23a1caf14f7ebf6830ab32bcaa50e Both the IPQ_APSS_5424 and IPQ_APSS_6018 symbols are using the same prompt which complicates to see that which option corresponds to which driver. Add a prefix to both prompts to make it easier to differentiate the two options. While at it, also fix a typo in the help text of the IPQ_APSS_5424 symbol. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://lore.kernel.org/r/20251113-clk-qcom-apss-ipq-prompt-v1-1-b62cf2142609@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Both the IPQ_APSS_5424 and IPQ_APSS_6018 symbols are using the same
prompt which complicates to see that which option corresponds to which
driver.

Add a prefix to both prompts to make it easier to differentiate the
two options.

While at it, also fix a typo in the help text of the IPQ_APSS_5424
symbol.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20251113-clk-qcom-apss-ipq-prompt-v1-1-b62cf2142609@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: apss-ipq5424: remove unused 'apss_clk' structure 2025-11-13T17:42:07+00:00 Gabor Juhos j4g8y7@gmail.com 2025-11-13T16:15:25+00:00 dc937f12e6c3488713de1262e37a30307ee9feac The locally defined 'apss_clk' structure is not used in the code, so remove that. Compile tested only. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://lore.kernel.org/r/20251113-ipq5424-remove-apss_clk-v1-1-e942e720cf99@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
The locally defined 'apss_clk' structure is not used in the code, so
remove that.

Compile tested only.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20251113-ipq5424-remove-apss_clk-v1-1-e942e720cf99@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: tcsrcc-glymur: Update register offsets for clock refs 2025-11-01T19:01:43+00:00 Taniya Das taniya.das@oss.qualcomm.com 2025-10-31T10:02:25+00:00 a4aa1ceb89f5c0d27a55671d88699cf5eae7331b Update the register offsets for all the clock ref branches to match the new address mapping in the TCSR subsystem. Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC") Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251031-tcsrcc_glymur-v1-1-0efb031f0ac5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Update the register offsets for all the clock ref branches to match the
new address mapping in the TCSR subsystem.

Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-tcsrcc_glymur-v1-1-0efb031f0ac5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>