linux-toradex.git/drivers/clk/renesas, branch master

Replace by more specific (c files)

2026-07-03T05:38:17+00:00

Replace the #include of  by the more specific
 where applicable. For most cases the include
can be dropped completely, only a few drivers need one or two headers
added.

Acked-by: Danilo Krummrich 
Acked-by: Takashi Sakamoto 
Acked-by: Bjorn Helgaas 
Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König (The Capable Hub)

clk: renesas: r9a08g045: Drop unused pm_domain header file

2026-05-28T13:09:54+00:00

The linux/pm_domain.h header is not used in this file.  Remove it to
keep the includes clean.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260524082657.19335-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r8a779g0: Add DSC clock

2026-05-28T13:09:54+00:00

Add the DSC module clock for Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: Marek Vasut 
Signed-off-by: Tomi Valkeinen 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260515-rcar-du-dsc-v3-1-164157820498@ideasonboard.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing

2026-05-25T09:52:48+00:00

Rename the internal loop iterator variable in the for_each_mod_clock()
macro from 'i' to '__i'.

The current naming conflicts with local loop variables named 'i' inside
code blocks that utilize the macro, triggering compiler warnings due to
variable shadowing:

  drivers/clk/renesas/rzg2l-cpg.c:1494:36: warning: declaration of `i` shadows a previous local [-Wshadow]
   1494 |                  for (unsigned int i = 0; i < clk->num_shared_mstop_clks; i++)

Using a unique identifier for the macro-internal iterator resolves the
shadowing warnings globally across all macro expansions.

Fixes: 3fd4a8bb4b63 ("clk: renesas: rzg2l: Add macro to loop through module clocks")
Signed-off-by: Lad Prabhakar 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260520092947.70596-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro

2026-05-25T09:51:38+00:00

Drop the unused DEF_G3S_MUX helper macro from the r9a08g045 CPG
driver.

Signed-off-by: Lad Prabhakar 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260520092516.69819-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones

2026-05-22T08:24:32+00:00

Rename RZG3L_PLL_STBY_OFFSET(), RZG3L_PLL_STBY_RESETB,
RZG3L_PLL_STBY_RESETB_WEN, RZG3L_PLL_MON_OFFSET(), RZG3L_PLL_MON_RESETB,
and RZG3L_PLL_MON_LOCK to their CPG_PLL_* equivalents to reflect that
these macros are not RZG3L-specific and are shared across SoCs.

Also fold CPG_PLL_MON_OFFSET() into rzg2l-cpg.c alongside the other
CPG_PLL_*_OFFSET() helpers introduced in previous patches.

No functional changes.

Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Biju Das 
Link: https://patch.msgid.link/20260519141518.389670-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro

2026-05-22T08:24:32+00:00

Replace the per-SoC G3S_PLL146_CONF() and G3L_PLL1467_CONF() macros with
a unified CPG_PLL_CONF(stby, setting) macro defined in rzg2l-cpg.h.

Drop the now-redundant GET_REG_SAMPLL_{CLK1, SETTING}() macros, replacing
the latter with CPG_PLL1_SETTING_OFFSET() using FIELD_GET() to extract the
offset value. Update RZG3L_PLL_{STBY,MON}_OFFSET() macros to derive
offsets directly from CPG_PLL_STBY_OFFSET().

No functional changes.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260519141518.389670-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Simplify SAM PLL configuration macro

2026-05-22T08:24:32+00:00

Replace the PLL146_CONF() macro and its associated CPG_SAMPLL_CLK{1,2}(n)
helpers with a single CPG_SAM_PLL_CONF(stby) macro that takes the PLL
standby register offset directly.

This removes the implicit coupling between PLL index n and register layout
and eliminates the now-redundant GET_REG_SAMPLL_CLK2() macro. The RZ/V2M
PLL4 definition is also updated to use the new macro with its explicit
standby offset (0x100), removing the local PLL4_CONF define.

No functional changes.

Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Biju Das 
Link: https://patch.msgid.link/20260519141518.389670-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r8a73a4: Add ZT/ZTR trace clocks

2026-05-15T09:30:51+00:00

Implement support for the ZT trace bus and ZTR trace clocks on R-Mobile
APE6.

Signed-off-by: Marek Vasut 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260502185557.93061-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a08g046: Add RSPI clocks and resets

2026-05-11T08:09:27+00:00

Add clock and reset definitions for the three RSPI (Serial Peripheral
Interface) channels on the RZ/G3L (R9A08G046) SoC.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260505071544.8965-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven