linux-toradex.git/drivers/clk/renesas, branch master

clk: renesas: Add support for RZ/G3L SoC

2026-03-26T18:45:48+00:00

The clock structure for RZ/G3L is almost identical to that of the RZ/G3S
SoC with more IP blocks such as LCDC, CRU, LVDS, and GPU.

Add minimal clock and reset entries required to boot the system on
Renesas RZ/G3L SMARC EVK and bind it with the RZ/G2L CPG core driver.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260324114329.268249-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Re-enable critical module clocks during resume

2026-03-26T18:40:20+00:00

After a suspend/resume cycle, critical module clocks (CLK_IS_CRITICAL)
may be left disabled as there is no owning driver to restore them,
unlike regular clocks.
Add rzg2l_mod_enable_crit_clock_init_mstop() which walks all module
clocks on resume, re-enables any critical clock found disabled, and then
restores the MSTOP state for clocks that have one via the existing
helper.  This replaces the direct call to rzg2l_mod_clock_init_mstop()
in rzg2l_cpg_resume(), preserving the correct clock-before-MSTOP restore
ordering.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260324114329.268249-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()

2026-03-26T18:40:17+00:00

Refactor the mstop initialisation logic in rzg2l_mod_clock_init_mstop()
into a dedicated helper function rzg2l_mod_clock_init_mstop_helper().
This decouples the logic for setting module stop state on disabled
clocks from the iteration loop, allowing it to be reused during resume
to re-enable critical clocks.

No functional change.

Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Biju Das 
Link: https://patch.msgid.link/20260324114329.268249-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add helper for mod clock enable/disable

2026-03-26T18:40:14+00:00

Refactor rzg2l_mod_clock_endisable() by extracting its logic into a new
helper function rzg2l_mod_clock_endisable_helper(), which accepts an
additional set_mstop_state boolean parameter.  This allows callers to
control whether the module stop state is updated alongside the clock
enable/disable operation.  No functional change for existing callers.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260324114329.268249-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries

2026-03-26T18:39:55+00:00

The RZ/G2L SoC family requires DMA resets to be deasserted for routing
some peripheral interrupts to the CPU. Asserting these resets after boot
would silently break interrupt delivery with no driver to restore them.

Mark the DMA resets as critical by adding them to the crit_resets table
in the SoC-specific rzg2l_cpg_info for r9a07g043, r9a07g044, and
r9a08g045, preventing __rzg2l_cpg_assert() from asserting them and
ensuring they are deasserted during probe and resume.

Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Biju Das 
Link: https://patch.msgid.link/20260324114329.268249-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add support for critical resets

2026-03-26T18:39:32+00:00

Some reset lines must remain deasserted at all times after boot, as
asserting them would disable critical system functionality with no
owning driver to restore them.  This mirrors the existing crit_mod_clks
mechanism which protects critical module clocks from being disabled.

On RZ/G2L family SoCs, the DMA reset must be remain deasserted for
routing some peripheral interrupts to CPU.

Add crit_resets and num_crit_resets fields to struct rzg2l_cpg_info to
allow SoC-specific data tables to declare reset IDs that must never be
asserted.

Introduce rzg2l_cpg_deassert_crit_resets() to iterate over all critical
resets and deassert them.  Call it both at probe time and during resume
to ensure critical peripherals are held out of reset after power-on and
suspend/resume cycles.

Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Biju Das 
Link: https://patch.msgid.link/20260324114329.268249-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}

2026-03-25T17:29:29+00:00

The Renesas RZ/V2N SoC (a.k.a. r9a09g056) comes with 4 watchdogs.

As it turns out, it only makes sense for Linux to have access to
WDT1.

Remove the clock and reset entries for WDT{0,2,3} to prevent
interfering with the CM33 core.

This change is harmless as only WDT1 is currently used in Linux,
there are no users for the WDT{0,2,3} IPs.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260324225239.19136-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a06g032: Enable watchdog reset sources

2026-03-25T17:29:00+00:00

The watchdog timeout is signaled using an interrupt and, on this
interrupt, a software initiated reset is performed.

This software initiated reset performs, in the end, a hardware system
reset using SWRST_REQ of RSTCTRL register.

The watchdog itself is able to control directly the hardware system
reset without any operation done by the interrupt handler. This feature
allows the watchdog to not depend on the software to reset the system
when a watchdog timeout occurs.

Indeed, when the watchdog timeout occurs, the watchdog requests a system
reset using its own hardware dedicated line but this reset source is
disabled at the reset controller level.

To benefit of this feature and be robust against software issues, enable
watchdogs reset sources.

Suggested-by: Wolfram Sang 
Signed-off-by: Herve Codina (Schneider Electric) 
Reviewed-by: Wolfram Sang 
Tested-by: Wolfram Sang 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260324120435.243641-2-herve.codina@bootlin.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: cpg-mssr: Use struct_size() helper

2026-03-25T17:28:38+00:00

struct_size() is what is normally used when a flexible array member is
present to avoid accidental mistakes.  pm_size is still needed for the
memcpy() call below.

Added __counted_by for extra runtime analysis.

Signed-off-by: Rosen Penev 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260324021103.13651-1-rosenp@gmail.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a09g047: Add PCIe clocks and reset

2026-03-20T10:17:15+00:00

Add necessary clocks and reset entries for the PCIe controller.

Reviewed-by: Geert Uytterhoeven 
Signed-off-by: John Madieu 
Reviewed-by: Claudiu Beznea 
Tested-by: Claudiu Beznea 
Tested-by: Lad Prabhakar  # RZ/V2N EVK
Link: https://patch.msgid.link/20260318085119.44717-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven