linux-toradex.git/drivers/clk/renesas, branch v6.13-rc3

clk: renesas: vbattb: Add VBATTB clock driver

2024-11-06T07:52:45+00:00

The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
by the RTC. The input to the VBATTB could be a 32KHz crystal
or an external clock device.

The HW block diagram for the clock generator is as follows:

           +----------+ XC   `\
RTXIN  --->|          |----->| \       +----+  VBATTCLK
           | 32K clock|      |  |----->|gate|----------->
           | osc      | XBYP |  |      +----+
RTXOUT --->|          |----->| /
           +----------+      ,

After discussions w/ Stephen Boyd the clock tree associated with this
hardware block was exported in Linux as:

vbattb-xtal
   xbyp
   xc
      mux
         vbattbclk

where:
- input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
- xc, xbyp are mux inputs
- mux is the internal mux
- vbattclk is the gate clock that feeds in the end the RTC

to allow selecting the input of the MUX though assigned-clock DT
properties, using the already existing clock drivers and avoid adding
other DT properties. If the crystal is connected on RTXIN,
RTXOUT pins the XC will be selected as mux input. If an external clock
device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
mux input.

The load capacitance of the internal crystal can be configured
with renesas,vbattb-load-nanofarads DT property.

Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Fix FOUTPOSTDIV clk

2024-11-03T10:48:39+00:00

While computing foutpostdiv_rate, the value of params->pl5_fracin
is discarded, which results in the wrong refresh rate. Fix the formula
for computing foutpostdiv_rate.

Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: Hien Huynh 
Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20241024134236.315289-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a08g045: Add power domain for RTC

2024-10-25T09:08:16+00:00

The RTC and VBATTB don't share the MSTOP control bit (but only the bus
clock and the reset signal). As the MSTOP control is modeled though power
domains add power domain support for the RTC device available on the
Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20241019084738.3370489-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe

2024-10-25T09:00:41+00:00

If the watchdog is part of a dedicated power domain (as it may be on
RZ/G3S) the watchdog PM domain need to be powered on in the watchdog
restart handler. Currently, only the clocks are enabled in the watchdog
restart handler. To be able to also power on the PM domain we need to
call pm_runtime_resume_and_get() on the watchdog restart handler, mark
the watchdog device as IRQ safe and register the watchdog PM domain
with GENPD_FLAG_IRQ_SAFE.

Register watchdog PM domain as IRQ safe. Along with it the always-on
PM domain (parent of the watchdog domain) was marked as IRQ safe.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Ulf Hansson 
Link: https://lore.kernel.org/20241015164732.4085249-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones

2024-10-25T09:00:33+00:00

For watchdog PM domain it is necessary to provide GENPD_FLAG_IRQ_SAFE flag
to be able to power on the watchdog PM domain from atomic context. For
this, adjust the current infrastructure to be able to provide GENPD_FLAG_*
for individual PM domains.

With this, remove the always_on flag from rzg2l_cpg_add_pm_domains() as
it is not necessary anymore.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Ulf Hansson 
Link: https://lore.kernel.org/20241015164732.4085249-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()

2024-10-25T08:59:38+00:00

Move the PM domain power on in rzg2l_cpg_pd_setup(). With this the
previously always-on power domains got
struct generic_pm_domain::{power_on, power_off} populated (and
registered with simple_qos_governor if #power-domain-cells = <1> and
with pm_domain_always_on_gov if #power-domain-cells = <0>). The values for
struct generic_pm_domain::{power_on, power_off} are now populated for
all registered domains but used by core only for the domains that can
use them (the PM domain should be non always-on and registered with
simple_qos_governor). Moreover, the power on/off functions check if the
mstop support is valid. The mstop is populated only by the RZ/G3S
initialization code at the moment.

This approach was chosen to keep the code simple and use the same code
across different implementations. There should be no issues with this
approach as the always on domains are registered with GENPD_FLAG_ALWAYS_ON
and the PM domain core takes care of it.

This approach allows doing further cleanups on the rzg2l_cpg power domain
registering code that will be handled by the next commit.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Ulf Hansson 
Link: https://lore.kernel.org/20241015164732.4085249-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks

2024-10-14T08:04:31+00:00

Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:

    ZCnφ = (PLL2VCO x 1/2) x mult/32

Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.

In Rev.0.70 of the documentation, the formula was corrected to:

    ZCnφ = (PLL2VCO x 1/4) x mult/32

As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion.  Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.

Reported-by: Vinh Nguyen 
Signed-off-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be

clk: renesas: r9a09g057: Add clock and reset entries for ICU

2024-10-07T08:33:51+00:00

Add clock and reset entries for the Renesas RZ/V2H(P) ICU IP block.

Signed-off-by: Lad Prabhakar 
Signed-off-by: Fabrizio Castro 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20240930145244.356565-4-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a09g057: Add CA55 core clocks

2024-10-07T08:32:56+00:00

Add CA55 core clocks which are derived from PLLCA55.

Signed-off-by: Lad Prabhakar 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20240918135957.290101-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: Remove duplicate and trailing empty lines

2024-10-01T07:13:38+00:00

Remove the duplicate and trailing empty lines. No functional change.

Signed-off-by: Marek Vasut 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20240908211056.230784-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven