linux-toradex.git/drivers/clk/rockchip, branch v4.10

Merge tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

2016-12-06T23:17:26+00:00

Pull rockchip clk driver updates from Heiko Stuebner:

A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP),
a fix making sure the cpuclk rate is actually valid, before trying to
set it and a copy-paste fix for the rk3399's testclk.

* tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add clock controller for rk1108
  dt-bindings: add documentation for rk1108 cru
  clk: rockchip: add dt-binding header for rk1108
  clk: rockchip: fix copy-paste error in rk3399 testclk
  clk: rockchip: validity should be checked prior to cpu clock rate change

clk: rockchip: add clock controller for rk1108

2016-11-16T11:37:37+00:00

Add the clock tree definition and driver for rk1108 SoC.

Signed-off-by: Shawn Lin 
Tested-by: Jacob Chen 
Signed-off-by: Heiko Stuebner

clk: rockchip: fix copy-paste error in rk3399 testclk

2016-11-16T10:57:29+00:00

Fix RK3368_* to RK3399_* for rk3399 clk_test clock.

Signed-off-by: Jianqun Xu 
Signed-off-by: Heiko Stuebner

Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

2016-11-15T02:38:35+00:00

Pull Rockchip clk driver updates from Heiko Stuebner:

PLL initialization for PLLs having both an integral and fractional mode
(rk3036, rk3399) does now take into account the mode that the PLL is
actually running at.

As always also some additional and optimized PLL rates for rk3066 and
rk3399, some additional clock ids for rk3066 and some additional clocks
on rk3399 are now sucessfully handled inside their respective driver.

* tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused
  clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree
  clk: rockchip: add 400MHz to rk3066 clock rates table
  clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399
  clk: rockchip: Use clock ids for cpu and peri clocks on rk3066
  clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
  clk: rockchip: add 533.25MHz to rk3399 clock rates table

clk: rockchip: validity should be checked prior to cpu clock rate change

2016-11-14T11:20:53+00:00

If validity is not checked prior to clock rate change, clk_set_rate(
cpu_clk, unsupported_rate) will return success, but the real clock rate
change operation is prohibited in post clock change event. Alough post
clock change event will report error due to unsupported clock rate is
set, but this error message is ignored by clock framework.

Signed-off-by: Elaine Zhang 
Tested-by: Rocky Hao 
Signed-off-by: Heiko Stuebner

clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused

2016-11-05T22:16:29+00:00

Rockchip RK3399 PLLs can be used in two separate modes: integral and
fractional. We can select between these two modes with the unambiguously
named DSMPD bit.

During boot, we check all PLL settings to confirm that they match our
PLL table for that frequency, and reinitialize the PLLs where they
don't. The settings checked for this include the fractional divider
field that is only used in fractional mode, even if we're in integral
mode (DSMPD = 1) and that field has no effect.

This patch changes the check to only compare the fractional divider if
we're actually in fractional mode. This way, we won't reinitialize the
PLL in cases where there's absolutely no reason for that, which may
avoid glitching child clocks that should better not be glitched (e.g.
PWM regulators).

Signed-off-by: Julius Werner 

[cloned the fix to the pretty similar rk3036 pll]
Signed-off-by: Heiko Stuebner

clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree

2016-11-05T22:12:55+00:00

Optimize rk3399 clocktree by removing CLK_IGNORE_UNUSED of some clocks.

clocks will managered by usb:
- clk_usbphy0_480m_src
- clk_usbphy1_480m_src
- clk_usbphy_480m

clocks will be managered by pvtm:
- clk_pvtm_core_l
- clk_pvtm_core_b
- clk_pvtm_ddr

clocks will be managered by dfi:
- pclk_ddr_mon
- clk_dfimon0_timer
- clk_dfimon1_timer
- aclk_dcf
- pclk_dcf

Signed-off-by: Jianqun Xu 
Signed-off-by: Heiko Stuebner

clk: rockchip: add 400MHz to rk3066 clock rates table

2016-11-05T22:11:01+00:00

We need this to init PLL_CPLL to 400MHz at boot.

Signed-off-by: Paweł Jarosz 
Signed-off-by: Heiko Stuebner

clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399

2016-11-01T23:24:11+00:00

Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.

Let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.

Signed-off-by: Xing Zheng 
Signed-off-by: Heiko Stuebner

clk: rockchip: Use clock ids for cpu and peri clocks on rk3066

2016-10-21T13:27:22+00:00

Add bindings for ACLK_CPU, HCLK_CPU, PCLK_CPU, ACLK_PERI, HCLK_PERI, PCLK_PERI.

We need this to init it's rate at boot time.

Signed-off-by: Paweł Jarosz 
Signed-off-by: Heiko Stuebner