linux-toradex.git/drivers/clk/rockchip, branch v4.4.156

clk: rockchip: Prevent calculating mmc phase if clock rate is zero

2018-05-30T05:49:14+00:00

[ Upstream commit 4bf59902b50012b1dddeeaa23b217d9c4956cdda ]

The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.

Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: initialize flags of clk_init_data in mmc-phase clock

2016-08-10T09:49:28+00:00

commit 595144c1141c951a3c6bb9004ae6a2bc29aad66f upstream.

The flags element of clk_init_data was never initialized for mmc-
phase-clocks resulting in the element containing a random value
and thus possibly enabling unwanted clock flags.

Fixes: 89bf26cbc1a0 ("clk: rockchip: Add support for the mmc clock phases using the framework")
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: free memory in error cases when registering clock branches

2016-05-11T09:21:12+00:00

commit 2467b6745e0ae9c6cdccff24c4cceeb14b1cce3f upstream.

Add free memeory if rockchip_clk_register_branch fails.

Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...")
Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk-divider: make sure read-only dividers do not write to their register

2016-05-11T09:21:11+00:00

commit 50359819794b4a16ae35051cd80f2dab025f6019 upstream.

Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.

On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.

To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.

The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.

Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks

2016-04-12T16:09:02+00:00

commit e8b63288b37dbb8457b510c9d96f6006da4653f6 upstream.

hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.

Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix hdmi_cec gate-register

2016-04-12T16:09:02+00:00

commit fd0c0740fac17a014704ef89d8c8b1768711ca59 upstream.

Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix parents of video encoder/decoder

2016-04-12T16:09:02+00:00

commit 0f28d98463498c61c61a38aacbf9f69e92e85e9d upstream.

The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix cpuclk core dividers

2016-04-12T16:09:02+00:00

commit c6d5fe2ca8286f35a79f7345c9378c39d48a1527 upstream.

Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster

2016-04-12T16:09:02+00:00

commit 535ebd428aeb07c3327947281306f2943f2c9faa upstream.

Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2015-11-05T20:59:36+00:00

Pull clk updates from Stephen Boyd:
 "The majority of the changes are driver updates and new device support.
  The core framework is mostly unchanged this time around, with only a
  couple patches to expose a clk provider API and make getting clk
  parent names from DT more robust.

  Driver updates:

   - Support for clock controllers found on Broadcom Northstar SoCs and
     bcm2835 SoC

   - Support for Allwinner audio clocks

   - A few cleanup patches for Tegra drivers and support for the highest
     DFLL frequencies on Tegra124

   - Samsung exynos7 fixes and improvements

   - i.Mx SoC updates to add a few missing clocks and keep debug uart
     clocks on during kernel intialization

   - Some mediatek cleanups and support for more subsystem clocks

   - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain
     controllers

   - A new driver for the Silabs si514 clock chip"

* tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (143 commits)
  clk: qcom: msm8960: Fix dsi1/2 halt bits
  clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks
  clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks
  clk: Add clk_hw_is_enabled() for use by clk providers
  clk: Add stubs for of_clk_*() APIs when CONFIG_OF=n
  clk: versatile-icst: fix memory leak
  clk: Remove clk_{register,unregister}_multiplier()
  clk: iproc: define Broadcom NS2 iProc clock binding
  clk: iproc: define Broadcom NSP iProc clock binding
  clk: ns2: add clock support for Broadcom Northstar 2 SoC
  clk: iproc: Separate status and control variables
  clk: iproc: Split off dig_filter
  clk: iproc: Add PLL base write function
  clk: nsp: add clock support for Broadcom Northstar Plus SoC
  clk: iproc: Add PWRCTRL support
  clk: cygnus: Convert all macros to all caps
  ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
  clk: imx31: add missing of_node_put
  clk: imx27: add missing of_node_put
  clk: si5351: add missing of_node_put
  ...