linux-toradex.git/drivers/clk/rockchip, branch v5.10-rc6

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2020-10-22T19:53:28+00:00

Pull clk updates from Stephen Boyd:
 "This contains no changes to the core framework. It is a collection of
  various clk driver updates.

  The biggest driver updates in terms of lines of code is the Allwinner
  driver, closely followed by the Qualcomm and Mediatek drivers. All of
  those hit high because we add so many lines of clk data. Coming in
  fourth place is i.MX which also adds a bunch of clk data. This
  accounts for the new driver additions this time around.

  Otherwise the patches are lots of little cleanups and fixes for
  various clk drivers that have baked in linux-next for a while. I
  suppose one highlight or theme is that more clk drivers are being
  updated to work as modules, which is interesting to see such critical
  SoC infrastructure work as a loadable module.

  New Drivers:
   - Support qcom SM8150/SM8250 video and display clks
   - Support Mediatek MT8167 clks
   - Add clock for CRC block found on vf610 SoCs
   - Add support for the Renesas R-Car V3U (R8A779A0) SoC
   - Add support for the VSP for Resizing clock on Renesas RZ/G1H
   - Support Allwinner A100 SoC clks

  Removed Drivers:
   - Remove i.MX21 clock driver, as i.MX21 platform support is being
     dropped

  Updates:
   - Change how qcom's display port clks work
   - Small non-critical fixes for TI clk driver
   - Remove various unused variables in clk drivers
   - Allow Rockchip clk driver to be a module
   - Remove most __clk_lookup() calls in Samsung drivers (yay!)
   - Support building i.MX ARMv8 platforms clock driver as module
   - Some kerneldoc fixes here and there
   - A couple of minor i.MX clk data corrections
   - Update audio clock inverter and fdiv2 flag on Amlogic g12
   - Make amlogic clk drivers configurable in Kconfig
   - Fix Renesas VSP clock names to match corrected hardware
     documentation
   - Sigma-delta modulation on Allwinner R40
   - Various fixes for at91 clk driver
   - Use semicolons instead of commas in some places
   - Mark some variables const so they can move to RO memory"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits)
  clk: imx8mq: Fix usdhc parents order
  clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
  clk: Restrict CLK_HSDK to ARC_SOC_HSDK
  clk: at91: sam9x60: support only two programmable clocks
  clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
  clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
  clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
  clk: ingenic: Use readl_poll_timeout instead of custom loop
  clk: ingenic: Use to_clk_info() macro for all clocks
  clk: bcm2835: add missing release if devm_clk_hw_register fails
  clk: at91: clk-sam9x60-pll: remove unused variable
  clk: at91: clk-main: update key before writing AT91_CKGR_MOR
  clk: at91: remove the checking of parent_name
  clk: clk-prima2: fix return value check in prima2_clk_init()
  clk: mmp2: Fix the display clock divider base
  clk: pxa: Constify static struct clk_ops
  clk: baikal-t1: Mark Ethernet PLL as critical
  clk: qoriq: modify MAX_PLL_DIV to 32
  clk: axi-clkgen: Set power bits for fractional mode
  clk: axi-clkgen: Add support for fractional dividers
  ...

clk: rockchip: Initialize hw to error to avoid undefined behavior

2020-10-08T02:08:38+00:00

We can get down to this return value from ERR_CAST() without
initializing hw. Set it to -ENOMEM so that we always return something
sane.

Fixes the following smatch warning:

drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'.
drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST'

Cc: Elaine Zhang 
Cc: Heiko Stuebner 
Fixes: 956060a52795 ("clk: rockchip: add support for half divider")
Reviewed-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

clk: rockchip: rk3399: Support module build

2020-09-22T13:16:54+00:00

support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.

Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20200914022316.24045-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner

clk: rockchip: fix the clk config to support module build

2020-09-22T13:16:38+00:00

use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark CONFIG_CLK_RK3399 to "tristate",
to support building Rk3399 SoC clock driver as module.

Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20200914022304.23908-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner

clk: rockchip: Export some clock common APIs for module drivers

2020-09-22T13:16:38+00:00

This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.

Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20200914022225.23613-5-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner

clk: rockchip: Export rockchip_register_softrst()

2020-09-22T13:16:38+00:00

This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..

Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20200914022225.23613-4-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner

clk: rockchip: Export rockchip_clk_register_ddrclk()

2020-09-22T13:16:37+00:00

This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..

Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20200914022225.23613-3-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner

clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls

2020-09-22T13:16:37+00:00

clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.

Reported-by: kernel test robot 
Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang 
Reviewed-by: Heiko Stuebner 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20200914022225.23613-2-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3308: drop unused mux_timer_src_p

2020-09-22T12:36:20+00:00

The parent names 'mux_timer_src_p' is not used:

  In file included from drivers/clk/rockchip/clk-rk3308.c:13:0:
  drivers/clk/rockchip/clk-rk3308.c:136:7: warning: ‘mux_timer_src_p’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20200916161740.14173-6-krzk@kernel.org
Signed-off-by: Heiko Stuebner

clk: rockchip: Fix initialization of mux_pll_src_4plls_p

2020-08-19T03:09:02+00:00

A new warning in Clang points out that the initialization of
mux_pll_src_4plls_p appears incorrect:

../drivers/clk/rockchip/clk-rk3228.c:140:58: warning: suspicious
concatenation of string literals in an array initialization; did you
mean to separate the elements with a comma? [-Wstring-concatenation]
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                              ^
                                                             ,
../drivers/clk/rockchip/clk-rk3228.c:140:48: note: place parentheses
around the string literal to silence warning
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                    ^
1 warning generated.

Given the name of the variable and the same variable name in rv1108, it
seems that this should have been four distinct elements. Fix it up by
adding the comma as suggested.

Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Link: https://github.com/ClangBuiltLinux/linux/issues/1123
Signed-off-by: Nathan Chancellor 
Link: https://lore.kernel.org/r/20200810044020.2063350-1-natechancellor@gmail.com
Reviewed-by: Heiko Stübner 
Signed-off-by: Stephen Boyd