linux-toradex.git/drivers/clk/rockchip, branch v6.11-rc3

clk: rockchip: rk3188: Drop CLK_NR_CLKS usage

2024-06-27T19:04:40+00:00

In order to get rid of CLK_NR_CLKS and be able to drop it from the
bindings, use rockchip_clk_find_max_clk_id helper to find the highest
clock id.

Signed-off-by: Johan Jonker 
Link: https://lore.kernel.org/r/1cd309fa-a4d3-4283-aa47-1330a40448a7@gmail.com
Signed-off-by: Heiko Stuebner

clk: rockchip: Switch to use kmemdup_array()

2024-06-23T20:10:48+00:00

Let the kememdup_array() take care about multiplication and possible
overflows.

Signed-off-by: Andy Shevchenko 
Link: https://lore.kernel.org/r/20240606161028.2986587-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3128: Add HCLK_SFC

2024-06-23T20:10:43+00:00

The SFC IP exists only in RK3128 version of the SoC, thus the clock gets
added to rk3128_clk_branches.

Signed-off-by: Alex Bee 
Link: https://lore.kernel.org/r/20240606143401.32454-6-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3128: Drop CLK_NR_CLKS usage

2024-06-08T13:56:35+00:00

In order to get rid of CLK_NR_CLKS and be able to drop it from the
bindings, use rockchip_clk_find_max_clk_id helper to find the highest
clock id.

Signed-off-by: Alex Bee 
Link: https://lore.kernel.org/r/20240606143401.32454-3-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks

2024-05-28T14:38:29+00:00

The DSI controller needs this clock to be enabled in order to be able to
access the registers. Make it critical for that purpose.

Signed-off-by: Alex Bee 
Link: https://lore.kernel.org/r/20240509140653.168591-5-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3128: Export PCLK_MIPIPHY

2024-05-28T14:38:26+00:00

Export the D-DHY's APB clock for usage in the DT. Also drop the
CLK_IGNORE_UNUSED-flag, as the clock will be enabled on demand.

Signed-off-by: Alex Bee 
Link: https://lore.kernel.org/r/20240509140653.168591-4-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3568: Add PLL rate for 724 MHz

2024-05-04T10:38:13+00:00

This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.

Signed-off-by: Lucas Stach 
Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de
Signed-off-by: Heiko Stuebner

clk: rockchip: Remove an unused field in struct rockchip_mmc_clock

2024-05-04T10:38:02+00:00

In "struct rockchip_mmc_clock", the 'id' field is unused.
Remove it.

Found with cppcheck, unusedStructMember.

Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/410bc0f86c7b9f1c80f8a4e9a2a028a9a6ee1ec0.1713970085.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: Add reset line for HDMI Receiver

2024-04-10T05:10:40+00:00

Export hdmirx_biu reset line required by the Synopsys
DesignWare HDMIRX Controller.

Signed-off-by: Shreeya Patel 
Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3568: Add missing USB480M_PHY mux

2024-04-10T05:10:17+00:00

The USB480M clock can source from a MUX that selects the clock to come
from either of the USB-phy internal 480MHz PLLs. These clocks are
provided by the USB phy driver.

Signed-off-by: David Jander 
Link: https://lore.kernel.org/r/20240404-clk-rockchip-rk3568-add-usb480m-phy-mux-v1-1-e8542afd58b9@pengutronix.de
Signed-off-by: Sascha Hauer 
Link: https://lore.kernel.org/r/20240405-clk-rk3568-usb480m-phy-mux-v1-2-6c89de20a6ff@pengutronix.de
Signed-off-by: Heiko Stuebner