linux-toradex.git/drivers/clk/rockchip, branch v6.15-rc7

clk: rockchip: Add clock controller for the RK3562

2025-03-02T16:51:51+00:00

Add the clock tree definition for the new RK3562 SoC.

Signed-off-by: Finley Xiao 
Signed-off-by: Tao Huang 
Signed-off-by: Sugar Zhang 
Signed-off-by: Kever Yang 
Link: https://lore.kernel.org/r/20250227105916.2340856-3-kever.yang@rock-chips.com
[dropped non-working module code, cleaned up init a bit to address
 build failure reported from kernel test robot
 Reported-by: kernel test robot 
 Closes: https://lore.kernel.org/oe-kbuild-all/202503021302.FjsycBI2-lkp@intel.com/ ]
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3528: Add reset lookup table

2025-02-27T19:08:25+00:00

In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver
for RK3528 SoC") only the dt-binding header was added for the reset
controller for the RK3528 SoC.

Add a reset lookup table generated from the SRST symbols used by vendor
linux-6.1-stan-rkr5 kernel to complete support for the reset controller.

Signed-off-by: Jonas Karlman 
Link: https://lore.kernel.org/r/20250227175302.2950788-1-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller driver for RK3528 SoC

2025-02-26T17:04:29+00:00

Add clock tree definition for RK3528. Similar to previous Rockchip
SoCs, clock controller of RK3528 is combined with the reset controller.
We omit the reset part for now since it's hard to test it without
support for other basic peripherals.

Signed-off-by: Yao Zi 
Link: https://lore.kernel.org/r/20250217061142.38480-8-ziyao@disroot.org
Signed-off-by: Heiko Stuebner

clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE

2025-02-26T17:04:29+00:00

RK3528 comes with a new PLL variant: its "PPLL", which mainly generates
clocks for the PCIe controller, operates in normal mode only. Let's
describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code.

Signed-off-by: Yao Zi 
Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent

2025-02-26T16:56:39+00:00

Correct the clk_ref_usb3otg parent to fix clock control for the usb3
controller on rk3328. Verified against the rk3328 trm, the rk3228h trm,
and the rk3328 usb3 phy clock map.

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Signed-off-by: Peter Geis 
Reviewed-by: Dragan Simic 
Link: https://lore.kernel.org/r/20250115012628.1035928-2-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3568: mark hclk_vi as critical

2025-02-26T16:53:39+00:00

The clock 'pclk_vi_niu' has a dependency on 'hclk_vi_niu' according
to the Technical Reference Manual section '2.8.6 NIU Clock gating
reliance'. However, this kind of dependency cannot be addressed
properly at the moment (until the support for linked clocks is
implemented for the RK3568).
As an intermediate solution, mark the hclk_vi as critical on the
Rockchip RK3568.

Suggested-by: Nicolas Frattaroli 
Signed-off-by: Michael Riesch 
Link: https://lore.kernel.org/r/20250210-rk3568-hclk-vi-v1-1-9ade2626f638@wolfvision.net
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066

2025-02-26T16:52:48+00:00

RK3066 has two "CIF" video capture interface blocks, reference the
newly added IDs for their PCLK clocks.

Signed-off-by: Val Packett 
Link: https://lore.kernel.org/r/20241205182954.5346-2-val@packett.cool
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: make refclko25m_ethX critical

2025-01-09T15:23:32+00:00

Ethernet phys normally need a 25MHz refclk input. On a lot of boards
this is done with a dedicated 25MHz crystal. But the rk3588 CRU also
provides a means for that via the refclko25m_ethX clock outputs that
can be used for that function.

The mdio bus normally probes devices on the bus at runtime, by reading
specific phy registers. This requires the phy to be running and thus
also being supplied by its reference clock.

While there exist the possibility and dt-binding to declare these
input clocks for each phy in the phy-dt-node, this is only relevant
_after_ the phy has been detected and during the drivers probe-run.

This results in a chicken-and-egg-problem. The refclks in the CRU are
running on boot of course, but phy-probing can very well happen after
clk_disable_unused has run.

In the past I tried to make clock-handling part of the mdio bus code [0]
but that wasn't very well received, due to it being specific to OF and
clocks with the consensus being that resources needed for detection
need to be enabled before.

So to make probing ethernet phys using the internal refclks possible,
make those 2 clocks critical.

[0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/

Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: drop RK3588_LINKED_CLK

2025-01-09T15:19:21+00:00

With the proper GATE_LINK support, we no longer need to keep the
linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL
flag for them.

Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20241211165957.94922-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner

clk: rockchip: implement linked gate clock support

2025-01-09T15:19:21+00:00

Recent Rockchip SoCs have a new hardware block called Native Interface
Unit (NIU), which gates clocks to devices behind them. These clock
gates will only have a running output clock when all of the following
conditions are met:

1. the parent clock is enabled
2. the enable bit is set correctly
3. the linked clock is enabled

To handle them this code registers them as a normal gate type clock,
which takes care of condition 1 + 2. The linked clock is handled by
using runtime PM clocks. Handling it via runtime PM requires setting
up a struct device for each of these clocks with a driver attached
to use the correct runtime PM operations. Thus the complete handling
of these clocks has been moved into its own driver.

Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner