<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/clk/samsung, branch v3.12.33</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks</title>
<updated>2014-01-15T23:31:42+00:00</updated>
<author>
<name>Andrew Bresticker</name>
<email>abrestic@chromium.org</email>
</author>
<published>2013-11-08T10:14:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=778b3b76c34292c7d27aa0faad5c9026a2cacf43'/>
<id>778b3b76c34292c7d27aa0faad5c9026a2cacf43</id>
<content type='text'>
commit 97c3557c3e0413efb1f021f582d1459760e22727 upstream.

The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker &lt;abrestic@chromium.org&gt;
Signed-off-by: Sachin Kamat &lt;sachin.kamat@linaro.org&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 97c3557c3e0413efb1f021f582d1459760e22727 upstream.

The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker &lt;abrestic@chromium.org&gt;
Signed-off-by: Sachin Kamat &lt;sachin.kamat@linaro.org&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock</title>
<updated>2014-01-15T23:31:42+00:00</updated>
<author>
<name>Abhilash Kesavan</name>
<email>a.kesavan@samsung.com</email>
</author>
<published>2013-12-11T11:57:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=801e517cf190f19c5cb2e62605d92524a9396be8'/>
<id>801e517cf190f19c5cb2e62605d92524a9396be8</id>
<content type='text'>
commit 2feed5aecf5f367b92bd6b6e92afe9e3de466907 upstream.

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.

Signed-off-by: Abhilash Kesavan &lt;a.kesavan@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 2feed5aecf5f367b92bd6b6e92afe9e3de466907 upstream.

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.

Signed-off-by: Abhilash Kesavan &lt;a.kesavan@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos5250: Add MDMA0 clocks</title>
<updated>2014-01-15T23:31:42+00:00</updated>
<author>
<name>Abhilash Kesavan</name>
<email>a.kesavan@samsung.com</email>
</author>
<published>2013-12-12T03:02:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f19053a2ddf64b1b98157e2d78c14b0cf5fb95c6'/>
<id>f19053a2ddf64b1b98157e2d78c14b0cf5fb95c6</id>
<content type='text'>
commit 8fb9aeb7a71ef4f3e0613d459a2e1366a7a90469 upstream.

Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.

Signed-off-by: Abhilash Kesavan &lt;a.kesavan@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 8fb9aeb7a71ef4f3e0613d459a2e1366a7a90469 upstream.

Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.

Signed-off-by: Abhilash Kesavan &lt;a.kesavan@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos5250: Fix ACP gate register offset</title>
<updated>2014-01-15T23:31:41+00:00</updated>
<author>
<name>Abhilash Kesavan</name>
<email>a.kesavan@samsung.com</email>
</author>
<published>2013-12-12T03:02:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c1adda6a9b2afa13e0e26a966ca355c69192dbc9'/>
<id>c1adda6a9b2afa13e0e26a966ca355c69192dbc9</id>
<content type='text'>
commit 3bf34666a0cce5234ac677ed2fbe5cea82c71329 upstream.

The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.

Signed-off-by: Abhilash Kesavan &lt;a.kesavan@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 3bf34666a0cce5234ac677ed2fbe5cea82c71329 upstream.

The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.

Signed-off-by: Abhilash Kesavan &lt;a.kesavan@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos4: Correct SRC_MFC register</title>
<updated>2014-01-15T23:31:41+00:00</updated>
<author>
<name>Seung-Woo Kim</name>
<email>sw0312.kim@samsung.com</email>
</author>
<published>2013-11-22T05:21:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=dda034c3ba2094dc414112706e1e3f353225ca07'/>
<id>dda034c3ba2094dc414112706e1e3f353225ca07</id>
<content type='text'>
commit 5fdd1b56be51b1ec4dbde5b213d649ac717442da upstream.

The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.

Signed-off-by: Seung-Woo Kim &lt;sw0312.kim@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 5fdd1b56be51b1ec4dbde5b213d649ac717442da upstream.

The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.

Signed-off-by: Seung-Woo Kim &lt;sw0312.kim@samsung.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux</title>
<updated>2013-09-09T22:49:04+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-09-09T22:49:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=bef4a0ab984662d4ccd68d431a7c4ef3daebcb43'/>
<id>bef4a0ab984662d4ccd68d431a7c4ef3daebcb43</id>
<content type='text'>
Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos5250: Simplify registration of PLL rate tables</title>
<updated>2013-09-06T20:34:05+00:00</updated>
<author>
<name>Tomasz Figa</name>
<email>t.figa@samsung.com</email>
</author>
<published>2013-08-26T17:09:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=22e9e7589e7bc6006af983f73e4a4057dbd9da66'/>
<id>22e9e7589e7bc6006af983f73e4a4057dbd9da66</id>
<content type='text'>
Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos4: Register PLL rate tables for Exynos4x12</title>
<updated>2013-09-06T20:34:01+00:00</updated>
<author>
<name>Tomasz Figa</name>
<email>t.figa@samsung.com</email>
</author>
<published>2013-08-26T17:09:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=efb19a85cb0b44c06ed5ff7c397341ab852148e5'/>
<id>efb19a85cb0b44c06ed5ff7c397341ab852148e5</id>
<content type='text'>
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos4: Register PLL rate tables for Exynos4210</title>
<updated>2013-09-06T20:33:57+00:00</updated>
<author>
<name>Tomasz Figa</name>
<email>t.figa@samsung.com</email>
</author>
<published>2013-08-26T17:09:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=5fadfc7ed37efe272983639f0d2f8c801303e796'/>
<id>5fadfc7ed37efe272983639f0d2f8c801303e796</id>
<content type='text'>
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: samsung: exynos4: Reorder registration of mout_vpllsrc</title>
<updated>2013-09-06T20:33:52+00:00</updated>
<author>
<name>Tomasz Figa</name>
<email>t.figa@samsung.com</email>
</author>
<published>2013-08-26T17:09:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4f7641f588dcc5f614a2dae18e614da7abd13604'/>
<id>4f7641f588dcc5f614a2dae18e614da7abd13604</id>
<content type='text'>
Since PLL input frequency must be known before PLL registration,
mout_vpllsrc clock which is a reference clock of VPLL must be registered
before VPLL.

This patch reorders clock registration to register mout_vpllsrc before
VPLL.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since PLL input frequency must be known before PLL registration,
mout_vpllsrc clock which is a reference clock of VPLL must be registered
before VPLL.

This patch reorders clock registration to register mout_vpllsrc before
VPLL.

Signed-off-by: Tomasz Figa &lt;t.figa@samsung.com&gt;
Signed-off-by: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Reviewed-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
