linux-toradex.git/drivers/clk/samsung, branch v4.9.9

clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUT

2016-10-28T00:26:54+00:00

The Exynos PMU node is an interrupt, clock and PMU (Power Management Unit)
controller, and these functionalities are supported by different drivers
that matches the same compatible strings.

Since commit 989eafd0b609 ("clk: core: Avoid double initialization of
clocks") the OF core flags clock controllers registered with the
CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same
compatible string will not be registered.

This prevents the PMU platform device to be created, so the Exynos PMU
driver is never probed. This breaks (among other things) Suspend-to-RAM.

Fix this by changing CLKOUT driver initialization method to
CLK_OF_DECLARE_DRIVER(), which doesn't clear the OF_POPULATED flag, so
later a platform device is created and the Exynos PMU platform driver
can be be probed properly.

Fixes: 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
Signed-off-by: Marek Szyprowski 
Reviewed-by: Javier Martinez Canillas 
Reviewed-by: Chanwoo Choi 
Signed-off-by: Stephen Boyd

clk: samsung: clk-exynos-audss: Fix module autoload

2016-10-17T22:21:48+00:00

If the driver is built as a module, autoload won't work because the module
alias information is not filled. So user-space can't match the registered
device with the corresponding module.

Export the module alias information using the MODULE_DEVICE_TABLE() macro.

Before this patch:

$ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias
alias:          platform:exynos-audss-clk

After this patch:

$ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias
alias:          platform:exynos-audss-clk
alias:          of:N*T*Csamsung,exynos5420-audss-clockC*
alias:          of:N*T*Csamsung,exynos5420-audss-clock
alias:          of:N*T*Csamsung,exynos5410-audss-clockC*
alias:          of:N*T*Csamsung,exynos5410-audss-clock
alias:          of:N*T*Csamsung,exynos5250-audss-clockC*
alias:          of:N*T*Csamsung,exynos5250-audss-clock
alias:          of:N*T*Csamsung,exynos4210-audss-clockC*
alias:          of:N*T*Csamsung,exynos4210-audss-clock

Fixes: 4d252fd5719b ("clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver")
Signed-off-by: Javier Martinez Canillas 
Reviewed-by: Krzysztof Kozlowski 
Tested-by: Krzysztof Kozlowski 
Signed-off-by: Stephen Boyd

clk: samsung: Add support for EPLL on exynos5410

2016-09-09T15:35:13+00:00

This patch adds code instantiating the EPLL, which is used as the
audio subsystem's root clock.
The requirement to specify the external root clock in clocks property
is documented.  Having the consumer 'clocks' property ensures proper
initialization order by explicitly specifying dependencies in DT.
It prevents situations when the SoC's clock controller driver has
initialized, the external oscillator clock is not yet registered
and setting clock frequencies through assigned-clock-rates property
doesn't work properly due to unknown external oscillator frequency.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Chanwoo Choi

clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup

2016-09-09T15:35:12+00:00

There is no need to log probe() completion in normal conditions
so the "setup completed" log is removed.

Signed-off-by: Sylwester Nawrocki

clk: samsung: clk-exynos-audss: Add exynos5410 compatible

2016-09-09T15:35:11+00:00

Exynos5410 Audio Subsystem Clock Controller, comparing to the already
supported IP block revisions, has additionally an I2S_MST divider
so a new compatible string is added.
It is not clear from the Exynos5410 User's Manual released on 2012.03.09
where in the clock tree the I2S_MST clock divider can be found exactly
so this clock is left unimplemented for now.

Signed-off-by: Sylwester Nawrocki

clk: samsung: clk-exynos-audss: controller variant handling rework

2016-09-09T15:35:10+00:00

Then variant handling is reworked to make the code simpler when
more variants are added.

Signed-off-by: Sylwester Nawrocki

clk: samsung: Use common registration function for pll2550x

2016-09-09T15:35:10+00:00

There is no such significant differences in pll2550x PLL type
to justify a separate registration function.  This patch adapts
exynos5440 driver to use the common function and removes
samsung_clk_register_pll2550x().

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Reviewed-by: Chanwoo Choi

clk: samsung: exynos5410: Expose the peripheral DMA gate clocks

2016-09-09T15:35:09+00:00

These clocks are needed in order to use the PL330 peripheral
DMA controllers.

Signed-off-by: Sylwester Nawrocki

clk: samsung: exynos5420: Add clocks for CMU_CDREX domain

2016-09-09T15:35:08+00:00

This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express
Controller) which generates the clocks for DRAM and NoC (Network on Chip)
bus.  There is differnet source of MUX_MX_MSPLL_CCORE between exynos5420
and exynos5422, so each MUX_MX_MSPLL_CCORE uses the different parent source
group.

Signed-off-by: Chanwoo Choi 
Signed-off-by: Sylwester Nawrocki

clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code

2016-09-09T15:35:07+00:00

This patch uses the samsung_cmu_register_one() to simplify code
and move the pll/mux/div/gate data to initconst section.

Signed-off-by: Chanwoo Choi 
Signed-off-by: Sylwester Nawrocki