linux-toradex.git/drivers/clk/samsung, branch v5.17-rc4

clk: samsung: Add initial Exynos7885 clock driver

2021-12-19T22:39:01+00:00

This is an initial implementation adding basic clocks, such as UART,
USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the
Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which
was made by Sam Protsenko, thus the copyright and author lines were
kept.

Bus clocks are enabled by default as well to avoid hangs while trying to
access CMU registers.

Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of
CMU_CORE, and most of CMU_PERI is implemented as of now.

Signed-off-by: David Virag 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20211206153124.427102-7-virag.david003@gmail.com

clk: samsung: clk-pll: Add support for pll1417x

2021-12-19T22:39:01+00:00

pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
It is similar enough to pll0822x that practically the same code can
handle both. The difference that's to be noted is that when defining a
pl1417x PLL, the "con" parameter of the PLL macro should be set to the
CON1 register instead of CON3, like this:

    PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
        PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
        NULL),

Signed-off-by: David Virag 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Reviewed-by: Sam Protsenko 
Link: https://lore.kernel.org/r/20211206153124.427102-6-virag.david003@gmail.com

clk: samsung: Make exynos850_register_cmu shared

2021-12-19T22:39:01+00:00

Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it
to a new file called "clk-exynos-arm64.c".

This should have no functional changes, but it will allow this code to
be shared between other arm64 Exynos SoCs, like the Exynos7885 and
possibly ExynosAuto V9.

Signed-off-by: David Virag 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Sam Protsenko 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20211206153124.427102-5-virag.david003@gmail.com

clk: samsung: exynos850: Add missing sysreg clocks

2021-12-19T22:25:53+00:00

System Register is used to configure system behavior, like USI protocol,
etc. SYSREG clocks should be provided to corresponding syscon nodes, to
make it possible to modify SYSREG registers.

While at it, add also missing PMU and GPIO clocks, which looks necessary
and might be needed for corresponding Exynos850 features soon.

Signed-off-by: Sam Protsenko 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Acked-by: Chanwoo Choi 
Link: https://lore.kernel.org/r/20211217161549.24836-3-semen.protsenko@linaro.org

clk: samsung: exynos850: Register clocks early

2021-11-22T21:58:43+00:00

Some clocks must be registered before init calls. For example MCT clock
(from CMU_PERI) is needed for MCT timer driver, which is registered
with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for
clk-exynos850 platform driver init, it's already too late. Inability to
get "mct" clock in MCT driver leads to kernel panic, as functions
registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver
can't be fixed either, as it's acting as a clock source and it's
essential to register it in start_kernel() -> time_init().

Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP
generates clocks needed for CMU_PERI, but it's already registered early.

While at it, let's cleanup the code a bit, by extracting everything
related to CMU initialization and registration to the separate function.

Similar issue was discussed at [1] and addressed in commit 1f7db7bbf031
("clk: renesas: cpg-mssr: Add early clock support"), as well as in
drivers/clk/mediatek/clk-mt2712.c.

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/

Signed-off-by: Sam Protsenko 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org

clk: samsung: exynos850: Keep some crucial clocks running

2021-11-22T09:52:00+00:00

Some clocks shouldn't be automatically disabled in clk_disable_unused(),
otherwise kernel hangs. Mark those clocks with:
  - CLK_IS_CRITICAL flag, when there won't be any consumers for that
    clock, but system can't function when it's gated
  - CLK_IGNORE_UNUSED flag, when consumer driver will be probably added
    later

That makes it possible to run the kernel without passing the
"clk_ignore_unused" param.

Next clocks were modified:
  - "gout_dpu_cmu_dpu_pclk":	CLK_IGNORE_UNUSED

    Will be enabled later in DSIM driver (Display Serial Interface
    Master).

  - "gout_gpio_peri_pclk":	CLK_IGNORE_UNUSED
    "gout_gpio_cmgp_pclk":	CLK_IGNORE_UNUSED
    "gout_gpio_hsi_pclk":	CLK_IGNORE_UNUSED

    Should be probably enabled in corresponding GPIO driver later, or
    made CLK_IS_CRITICAL. "gout_gpio_peri_clk" is actually used by LEDs
    on Exynos850-based dev board, so kernel hangs if this clock is not
    running. Other clocks were marked as "ignore unused" to prevent
    similar issues for other use cases or boards that might be added
    later.

  - "gout_cci_aclk":		CLK_IS_CRITICAL

    CCI (Cache Coherent Interconnect): obviously is critical.

  - "gout_gic_clk":		CLK_IS_CRITICAL

    GIC (Generic Interrupt Controller): obviously is critical.

Signed-off-by: Sam Protsenko 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20211121232741.6967-7-semen.protsenko@linaro.org

clk: samsung: exynos850: Implement CMU_CMGP domain

2021-11-22T09:13:18+00:00

CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO).
CMGP module encapsulates next blocks:
  - 8 GPIO lines
  - 1 GPADC
  - 2 USI blocks, each can be configured to provide one of
    UART/SPI/HSI2C serial interfaces

Signed-off-by: Sam Protsenko 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20211121232741.6967-5-semen.protsenko@linaro.org

clk: samsung: exynos850: Implement CMU_APM domain

2021-11-22T09:13:18+00:00

CMU_APM clock domain provides clocks for APM IP-core (Active Power
Management). According to Exynos850 TRM, CMU_APM generates I3C, Mailbox,
Speedy, Timer, WDT, RTC and PMU clocks for BLK_ALIVE.

This patch adds next clocks:
  - bus clocks in CMU_TOP needed for CMU_APM
  - all internal CMU_APM clocks
  - leaf clocks for I3C, Speedy and RTC IP-cores
  - bus clocks for CMU_CMGP and CMU_CHUB

CMU_APM doesn't belong to Power Domains, but platform driver is used for
its registration to keep its bus clock always running. Otherwise rtc-s3c
driver disables that clock and system freezes.

Signed-off-by: Sam Protsenko 
Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Acked-by: Chanwoo Choi 
Link: https://lore.kernel.org/r/20211121232741.6967-3-semen.protsenko@linaro.org

clk: samsung: Update CPU clk registration

2021-11-20T13:22:49+00:00

Convert the remaining exynos clock drivers to use
samsung_clk_register_cpu() or if possible use samsung_cmu_register_one().
With this we can now make exynos_register_cpu_clock() a static function
so that future CPU clock registration changes will use the samsung common
clock driver.

The main benefit of this change is that it standardizes the CPU clock
registration for the samsung clock drivers.

Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com
Signed-off-by: Will McVicker 
Tested-by: Krzysztof Kozlowski 
Reviewed-by: Krzysztof Kozlowski 
[snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c]
Reported-by: kernel test robot 
Signed-off-by: Sylwester Nawrocki

clk: samsung: Remove meaningless __init and extern from header files

2021-11-19T18:32:36+00:00

Remove useless __init atrribute and unneeded extern qualifier in function
declarations in header files.

Signed-off-by: Sylwester Nawrocki 
Reviewed-by: Krzysztof Kozlowski 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20211015151425.29743-1-s.nawrocki@samsung.com