linux-toradex.git/drivers/clk/socfpga, branch toradex_vf_4.1

Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga

2014-05-13T02:11:13+00:00

Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden.

clk: socfpga: add divider registers to the main pll outputs

2014-05-12T17:27:22+00:00

The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.

This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.

Signed-off-by: Dinh Nguyen

clk: socfpga: fix clock driver for 3.15

2014-04-30T18:44:01+00:00

commit [1771b10d6 clk: respect the clock dependencies in of_clk_init]
exposed a flaw in the socfpga clock driver and prevents the platform
from booting on 3.15-rc1.

Because the "altr,clk-mgr" is not really a clock, it should not be using
CLK_OF_DECLARE, instead we should be mapping the clk-mgr's base address
one of the functional clock init function. Use the socfpga_pll_init function
to map the clk_mgr_base_addr as this clock should always be initialized first.

Signed-off-by: Dinh Nguyen 
Tested-by: Pavel Machek

clk: socfpga: Fix section mismatch warning

2014-03-19T06:42:35+00:00

WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_pll_init()
The variable socfpga_child_clocks references
the function __init socfpga_pll_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_periph_init()
The variable socfpga_child_clocks references
the function __init socfpga_periph_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_gate_init()
The variable socfpga_child_clocks references
the function __init socfpga_gate_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

Reported-by: Mike Turquette 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Mike Turquette

clk: socfpga: Support multiple parents for the pll clocks

2014-02-26T20:23:40+00:00

The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen 
Cc: Steffen Trumtrar 
Signed-off-by: Mike Turquette

clk: socfpga: Fix integer overflow in clock calculation

2014-02-26T20:23:29+00:00

Use 64-bit integer for calculating clock rate. Also use do_div for the
64-bit division.

Signed-off-by: Graham Moore 
Signed-off-by: Dinh Nguyen 
Cc: Steffen Trumtrar 
Signed-off-by: Mike Turquette

clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

2014-02-18T22:08:14+00:00

The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.

Signed-off-by: Dinh Nguyen 
Acked-by: Zhangfei Gao 
Acked-by: Jaehoon Chung 
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
    prepare function to the gate clk that will toggle clock phase setting.
    Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
    set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
    loaded after the clock driver.
v2: Use the syscon driver

clk: socfpga: split clk code

2014-02-18T22:08:13+00:00

Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.

The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.

Signed-off-by: Steffen Trumtrar 
Signed-off-by: Dinh Nguyen

clk: socfpga: fix define typo

2014-02-18T22:08:12+00:00

It should be SOCFPGA instead of SOCFGPA.

Signed-off-by: Steffen Trumtrar 
Signed-off-by: Dinh Nguyen

clk: socfpga: remove unused field

2014-02-18T22:08:10+00:00

The clk_name field from the socfpga_clk struct is unused.
Remove it.

Signed-off-by: Steffen Trumtrar 
Signed-off-by: Dinh Nguyen