linux-toradex.git/drivers/clk/st, branch v3.16.7

clk: st: Terminate of match table

2014-05-28T19:08:53+00:00

Failure to terminate this match table can lead to boot failures
depending on where the compiler places the match table.

Cc: Gabriel FERNANDEZ 
Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette

clk: st: Fix memory leak

2014-05-23T22:13:32+00:00

When it fails to allocate div, gate should be free'd before return

Signed-off-by: Valentin Ilie 
Signed-off-by: Mike Turquette

clk: st: Support for A9 MUX clocks

2014-03-25T22:59:23+00:00

The patch supports the A9-mux clocks used by ClockGenA9

A9-mux clock : Multiplexer inside ClockGenA9. A9 clock can be driven by
either PLL or External clock (with an optional divide-by-2). This is
implemented as 3-parent clock : PLL, Ext-clk OR Ext-clk/2

Signed-off-by: Pankaj Dev 
Signed-off-by: Mike Turquette

clk: st: Support for ClockGenA9/DDR/GPU

2014-03-25T22:59:17+00:00

The patch added support for DT registration of ClockGenA9/DDR/GPU

ClockgenA9/DDR : It includes c32 type PLL (also in ClockgenA1x), hence
only CLK_OF_DECLARE implementation is required.

ClockgenGPU : It includes c65 type PLL (also in ClockgenAx), hence
only CLK_OF_DECLARE implementation is required.

Signed-off-by: Pankaj Dev 
Signed-off-by: Gabriel Fernandez 
Signed-off-by: Mike Turquette

clk: st: Support for QUADFS inside ClockGenB/C/D/E/F

2014-03-25T22:59:09+00:00

The patch supports the 216/432/660 type Quad Frequency Synthesizers
used by ClockGenB/C/D/E/F

QUADFS clock : It includes support for all 216/432/660 type Quad
Frequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock,
with clock rate calculated reading H/w settings done at BOOT.

QuadFS have 4 outputs : chan0 chan1 chan2 chan3

Signed-off-by: Pankaj Dev 
Signed-off-by: Gabriel Fernandez 
Signed-off-by: Mike Turquette

clk: st: Support for VCC-mux and MUX clocks

2014-03-25T22:59:02+00:00

The patch supports the VCC-mux and MUX clocks used by ClockGenC/F

VCC-mux clock : Divider-Multiplexer-Gate inside ClockGenC/F
It includes support for each channel : 4-parent Multiplexer, Post Divide
by 1, 2, 4 or 8, Gate to switch OFF the output channel. The clock is
implemented using generic clocks implemented in the kernel clk_divider, clk_mux,
clk_gate and clk_composite (to combine all)

MUX clock : 2-parent clock used inside ClockGenC/F. The clock is implemented
using generic clocks implemented in the kernel clk_mux.

Signed-off-by: Pankaj Dev 
Signed-off-by: Gabriel Fernandez 
Signed-off-by: Mike Turquette

clk: st: Support for PLLs inside ClockGenA(s)

2014-03-25T22:58:56+00:00

The patch supports the c65/c32 type PLLs used by ClockGenA(s)

PLL clock : It includes support for all c65/c32 type PLLs
inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock,
with clock rate calculated reading H/w settings done at BOOT.

c65 PLLs have 2 outputs : HS and LS
c32 PLLs have 1-4 outputs : ODFx

Signed-off-by: Pankaj Dev 
Signed-off-by: Gabriel Fernandez 
Signed-off-by: Mike Turquette

clk: st: Support for DIVMUX and PreDiv Clocks

2014-03-25T22:58:47+00:00

The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s)

DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s)
It includes support for each channel : 3-parent Multiplexer,
Divider for each Parent, Gate to switch OFF the output channel. The
clock is implemented using generic clocks implemented in the kernel
clk_divider and clk_mux.

PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide
the oscillator clock by factor-of-16. The clock is implemented using
generic clocks implemented in the kernel clk_divider.

Signed-off-by: Pankaj Dev 
Signed-off-by: Gabriel Fernandez 
Signed-off-by: Mike Turquette