linux-toradex.git/drivers/clk/sunxi-ng, branch v4.9.128

clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops

2018-03-28T16:39:20+00:00

commit 5682e268350f9eccdbb04006605c1b7068a7b323 upstream.

When support for the A31/A31s CCU was first added, the clock ops for
the CLK_OUT_* clocks was set to the wrong type. The clocks are MP-type,
but the ops was set for div (M) clocks. This went unnoticed until now.
This was because while they are different clocks, their data structures
aligned in a way that ccu_div_ops would access the second ccu_div_internal
and ccu_mux_internal structures, which were valid, if not incorrect.

Furthermore, the use of these CLK_OUT_* was for feeding a precise 32.768
kHz clock signal to the WiFi chip. This was achievable by using the parent
with the same clock rate and no divider. So the incorrect divider setting
did not affect this usage.

Commit 946797aa3f08 ("clk: sunxi-ng: Support fixed post-dividers on MP
style clocks") added a new field to the ccu_mp structure, which broke
the aforementioned alignment. Now the system crashes as div_ops tries
to look up a nonexistent table.

Reported-by: Philipp Rossak 
Tested-by: Philipp Rossak 
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: 
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER

2018-02-25T10:05:50+00:00

commit aa01338c018469274848a973bcbd287ef341937c upstream.

With CONFIG_RESET_CONTROLLER=n we get the following link error in the
sunxi-ng clk driver:

drivers/built-in.o: In function `sunxi_ccu_probe':
mux-core.c:(.text+0x12fe68): undefined reference to 'reset_controller_register'
mux-core.c:(.text+0x12fe68): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol 'reset_controller_register'

Fix this by adding the appropriate select statement.

Signed-off-by: Tobias Regnery 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision

2017-12-25T13:23:45+00:00

[ Upstream commit 7f3ed79188f2f094d0ee366fa858857fb7f511ba ]

The HDMI DDC clock found in the CCU is the parent of the actual DDC
clock within the HDMI controller. That clock is also named "hdmi-ddc".

Rename the one in the CCU to "ddc". This makes more sense than renaming
the one in the HDMI controller to something else.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: fix PLL_CPUX adjusting on A33

2017-11-30T08:39:11+00:00

[ Upstream commit 790d929b540661945d1c70652ffb602c5c06ad85 ]

When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high,
and the system hangs.

Add a notifier to avoid this situation by temporarily switching to a
known stable 24 MHz oscillator.

Signed-off-by: Icenowy Zheng 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: A31: Fix spdif clock register

2017-11-30T08:39:11+00:00

[ Upstream commit 70421257c068b91476e70cade15fca68045d0693 ]

As the SPDIF was rarely documented on the earlier Allwinner SoCs
it was assumed that it had a similar clock register to the one
described in the H3 User Manual.

However this is not the case and it looks to shares the same setup
as the I2S clock registers.

Signed-off-by: Marcus Cooper 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: Check kzalloc() for errors and cleanup error path

2017-11-08T09:08:35+00:00

[ Upstream commit 5d806f9fc8e63d7a44e0fd1ef26a7c27efae0e51 ]

This kzalloc() could fail. Let's bail out with -ENOMEM here
instead of NULL dereferencing. That silences static checkers. We
should also cleanup on the error path even though this function
returning an error probably means the system won't boot.

Cc: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: fix PLL_CPUX adjusting on H3

2017-10-08T08:26:02+00:00

[ Upstream commit a43c96427e713bea94e9ef50e8be1f493afc0691 ]

When adjusting PLL_CPUX on H3, the PLL is temporarily driven
too high, and the system becomes unstable (oopses or hangs).

Add a notifier to avoid this situation by temporarily switching
to a known stable 24 MHz oscillator.

Signed-off-by: Ondrej Jirman 
Tested-by: Lutz Sammer 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

2017-06-29T11:00:27+00:00

commit 38b8f823864707eb1cf331d2247608c419ed388c upstream.

The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.

Reported-by: Bob Ham 
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

2017-03-30T07:41:26+00:00

commit ac8616e4c81dded650dfade49a7da283565d37ce upstream.

The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.

This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.

Fixes: 2ab836db5097 ("clk: sunxi-ng: Add M-P factor clock support")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock

2017-03-30T07:41:26+00:00

commit 9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d upstream.

The enable bit offset for the hdmi-ddc module clock is wrong. It is
pointing to the main hdmi module clock enable bit.

Reported-by: Bob Ham 
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman