linux-toradex.git/drivers/clk/sunxi/Makefile, branch v4.5

clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver

2015-12-09T09:17:22+00:00

The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
instead of through a PRCM mfd device and subdevices for each clock
and reset control. As such we need a CLK_OF_DECLARE version of
the sun8i-a23-apb0-clk driver.

Also, build it for sun9i/A80, and not just for configurations with
MFD_SUN6I_PRCM enabled.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i

2015-12-08T10:05:27+00:00

The video engine has its own special module clock, consisting of a clock
gate, configurable dividers, and a reset control.

On later (sun[68]i) families, the reset control is moved out of this
piece of hardware and grouped with reset controls of other peripherals.

Signed-off-by: Chen-Yu Tsai 
Tested-by: Jens Kuske 
Signed-off-by: Maxime Ripard

clk: sunxi: Add H3 clocks support

2015-12-08T08:11:53+00:00

The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske 
Acked-by: Rob Herring 
Signed-off-by: Maxime Ripard

clk: sunxi: Add sun9i A80 cpus (cpu special) clock support

2015-12-01T13:06:47+00:00

The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree. This clock includes a pre-
divider on one of its inputs. For now we are using a custom clock
driver for it. In the future we may want to develop a generalized
driver for these types of clocks, which also includes the AHB clock
driver on sun[5678]i.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
Signed-off-by: Maxime Ripard

clk: sunxi: mod1 clock support

2015-10-21T19:51:29+00:00

The module 1 type of clocks consist of a gate and a mux and are used on
the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
SPDIF. This commit adds support for them on the sunxi clock driver.

Signed-off-by: Emilio López 
Signed-off-by: Hans de Goede 
Signed-off-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai

clk: sunxi: codec clock support

2015-10-21T19:51:28+00:00

The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
parent. Add a driver for such a clock.

Signed-off-by: Emilio López 
Signed-off-by: Hans de Goede 
Signed-off-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai

clk: sunxi: Add a driver for the PLL2

2015-10-21T19:51:27+00:00

The PLL2 on the A10 and later SoCs is the clock used for all the audio
related operations.

This clock has a somewhat complex output tree, with three outputs (2X, 4X
and 8X) with a fixed divider from the base clock, and an output (1X) with a
post divider.

However, we can simplify things since the 1X divider can be fixed, and we
end up by having a base clock not exposed to any device (or at least
directly, since the 4X output doesn't have any divider), and 4 fixed
divider clocks that will be exposed.

This clock seems to have been introduced, at least in this form, in the
revision B of the A10, but we don't have any information on the clock used
on the revision A.

Signed-off-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai

clk: sunxi: Add a simple gates driver

2015-08-12T07:59:15+00:00

The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.

Move this code in a new driver that handles all the gates array and solves
both these issues.

Signed-off-by: Maxime Ripard 
Signed-off-by: Michael Turquette 
[sboyd@codeaurora.org: Include clk.h for consumer API usage]
Signed-off-by: Stephen Boyd

clk: sunxi: Move USB clocks to separate file

2015-02-23T08:25:54+00:00

The USB clocks originally shared code with the gates clocks, but had
additional reset controllers. Move these to a separate file. This will
allow us to add new support for slightly different USB clocks, such as
on the A80, without affecting gates clocks, and also facilitate the
migration of gates clocks to a generic solution.

This also cleans up the USB clocks code slightly, such as adding
newlines, getting rid of the unused clkdev call, using a simple
u32 instead of BITMAP for the clock masks, using BIT() macro to
declare the clock bitmasks, and using of_io_request_and_map() to
get the I/O address.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add driver for A80 MMC config clocks/resets

2015-01-20T16:14:38+00:00

On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard