linux-toradex.git/drivers/clk/tegra/Makefile, branch master

clk: tegra: Support runtime PM and power domain

2021-12-15T17:55:21+00:00

The Clock-and-Reset controller resides in a core power domain on NVIDIA
Tegra SoCs.  In order to support voltage scaling of the core power domain,
we hook up DVFS-capable clocks to the core GENPD for managing of the
GENPD's performance state based on the clock changes.

Some clocks don't have any specific physical hardware unit that backs
them, like root PLLs and system clock and they have theirs own voltage
requirements.  This patch adds new clk-device driver that backs the clocks
and provides runtime PM functionality for them.  A virtual clk-device is
created for each such DVFS-capable clock at the clock's registration time
by the new tegra_clk_register() helper.  Driver changes clock's device
GENPD performance state based on clk-rate notifications.

In result we have this sequence of events:

  1. Clock driver creates virtual device for selective clocks, enables
     runtime PM for the created device and registers the clock.
  2. Clk-device driver starts to listen to clock rate changes.
  3. Something changes clk rate or enables/disables clk.
  4. CCF core propagates the change through the clk tree.
  5. Clk-device driver gets clock rate-change notification or GENPD core
     handles prepare/unprepare of the clock.
  6. Clk-device driver changes GENPD performance state on clock rate
     change.
  7. GENPD driver changes voltage regulator state change.
  8. The regulator state is committed to hardware via I2C.

We rely on fact that DVFS is not needed for Tegra I2C and that Tegra I2C
driver already keeps clock always-prepared.  Hence I2C subsystem stays
independent from the clk power management and there are no deadlock spots
in the sequence.

Currently all clocks are registered very early during kernel boot when the
device driver core isn't available yet.  The clk-device can't be created
at that time.  This patch splits the registration of the clocks in two
phases:

  1. Register all essential clocks which don't use RPM and are needed
     during early boot.

  2. Register at a later boot time the rest of clocks.

This patch adds power management support for Tegra20 and Tegra30 clocks.

Reviewed-by: Ulf Hansson 
Tested-by: Peter Geis  # Ouya T30
Tested-by: Paul Fertser  # PAZ00 T20
Tested-by: Nicolas Chauvet  # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar  # Ouya T30
Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

memory: tegra124-emc: Make driver modular

2021-01-05T17:00:09+00:00

Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.

Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete callbacks. similarly to what is
done for the Tegra20/30 EMC drivers.

Tested-by: Nicolas Chauvet 
Signed-off-by: Dmitry Osipenko 
Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

clk: tegra: Add custom CCLK implementation

2020-05-12T20:48:42+00:00

CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports
multiple parents, it has internal clock divider and a clock skipper.
PLLX is the main CCLK parent that provides clock rates above 1GHz and it
has special property such that the CCLK's internal divider is set into
bypass mode when PLLX is selected as a parent for CCLK.

This patch forks generic Super Clock into CCLK implementation which takes
into account all CCLK specifics. The proper CCLK implementation is needed
by the upcoming Tegra20 CPUFreq driver update that will allow to utilize
the generic cpufreq-dt driver by moving intermediate clock selection into
the clock driver.

Note that technically this patch could be squashed into clk-super.c, but
it is cleaner to have a separate source file. Also note that currently all
CCLKLP bits are left in the clk-super.c and only CCLKG is supported by
clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits,
but CCLKLP is not used by anything in kernel and thus better not to touch
it for now.

Acked-by: Peter De Schrijver 
Tested-by: Peter Geis 
Tested-by: Marcel Ziswiler 
Tested-by: Jasper Korten 
Tested-by: David Heidelberg 
Tested-by: Nicolas Chauvet 
Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

clk: tegra: Implement Tegra210 EMC clock

2020-05-12T20:48:42+00:00

The EMC clock needs to carefully coordinate with the EMC controller
programming to make sure external memory can be properly clocked. Do so
by hooking up the EMC clock with an EMC provider that will specify which
rates are supported by the EMC and provide a callback to use for setting
the clock rate at the EMC.

Based on work by Peter De Schrijver .

Signed-off-by: Joseph Lo 
Signed-off-by: Thierry Reding

clk: tegra: Rename Tegra124 EMC clock source file

2020-05-12T20:48:41+00:00

This code is only used on Tegra124, so rename it accordingly to make it
more consistent with other file names.

While at it, also get rid of the TEGRA_CLK_EMC Kconfig symbol that's
really just an alias for TEGRA124_EMC.

Signed-off-by: Thierry Reding

clk: tegra: Remove tegra_pmc_clk_init along with clk ids

2020-03-12T10:34:04+00:00

Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,
clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct
PMC register access during clk_ops and these PMC register read and write
access will not happen when PMC is in secure mode.

Any direct PMC register access from non-secure world will not go
through.

All the PMC clocks are moved to Tegra PMC driver with PMC as a clock
provider.

This patch removes tegra_pmc_clk_init along with corresponding clk ids
from Tegra clock driver.

Tested-by: Dmitry Osipenko 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Sowjanya Komatineni 
Signed-off-by: Thierry Reding

clk: tegra: Add Tegra20/30 EMC clock implementation

2019-11-11T13:01:22+00:00

A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers, it is not available using
the generic clock implementation because only the Memory Controller driver
is aware of what clock rates are actually available for a particular
device. EMC drivers will have to register a Tegra-specific CLK-API
callback which will perform rounding of a requested rate. EMC clock users
won't be able to request EMC clock by getting -EPROBE_DEFER until EMC
driver is probed and the callback is set up.

The functionality is somewhat similar to the clk-emc.c which serves
Tegra124+ SoCs. The later HW generations support more parent clock sources
and the HW configuration / integration with the EMC drivers differs a tad
from the older gens, hence it's not really worth to try to squash
everything into a single source file.

Acked-by: Peter De Schrijver 
Signed-off-by: Dmitry Osipenko 
Acked-by: Stephen Boyd 
Signed-off-by: Thierry Reding

clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210

2019-02-06T13:29:37+00:00

Tegra210 has a DFLL as well and can share the majority of the code with
the Tegra124 implementation. So build the same code for both platforms.

Signed-off-by: Peter De Schrijver 
Signed-off-by: Joseph Lo 
Acked-by: Jon Hunter 
Acked-by: Stephen Boyd 
Signed-off-by: Thierry Reding

clk: tegra: Add sdmmc mux divider clock

2018-07-25T20:45:09+00:00

Add a clock type to model the sdmmc switch divider clocks which have paths
to source clocks bypassing the divider (Low Jitter paths). These
are handled by selecting the lj path when the divider is 1 (ie the
rate is the parent rate), otherwise the normal path with divider
will be selected. Otherwise this clock behaves as a normal peripheral
clock.

Signed-off-by: Peter De-Schrijver 
Signed-off-by: Aapo Vienamo 
Acked-by: Peter De Schrijver 
Acked-by: Jon Hunter 
Signed-off-by: Stephen Boyd

clk: tegra: Refactor fractional divider calculation

2018-07-25T20:43:34+00:00

Move this to a separate file so it can be used to calculate the sdmmc
clock dividers.

Signed-off-by: Peter De-Schrijver 
Signed-off-by: Aapo Vienamo 
Acked-by: Peter De Schrijver 
Acked-by: Jon Hunter 
Signed-off-by: Stephen Boyd