linux-toradex.git/drivers/clk/tegra/clk-pll.c, branch v3.13.9

clk: tegra: Use override bits when needed

2013-06-12T01:00:32+00:00

PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE
is set.

Signed-off-by: Peter De Schrijver 
Tested-by: Stephen Warren 
Acked-by: Stephen Warren 
Signed-off-by: Mike Turquette

clk: tegra: fix pllre initilization

2013-06-12T00:43:51+00:00

The PLLRE flags weren't set correctly. Fixed in this patch.

Signed-off-by: Peter De Schrijver 
Tested-by: Stephen Warren 
Acked-by: Stephen Warren 
Signed-off-by: Mike Turquette

clk: tegra: allow PLL m,n,p init from SoC files

2013-06-12T00:38:39+00:00

The m,n,p fields don't have the same bit offset and width across all PLLs.
This patch allows SoC specific files to indicate the offset and width.

Signed-off-by: Peter De Schrijver 
Tested-by: Stephen Warren 
Acked-by: Stephen Warren 
Signed-off-by: Mike Turquette

clk: tegra: pllc and pllxc should use pdiv_map

2013-06-11T23:15:22+00:00

The pllc and pllxc code weren't always using the correct pdiv_map to
map between the post divider value and the hw p field. This could result
in illegal values being programmed in the hw.

Signed-off-by: Peter De Schrijver 
Tested-by: Stephen Warren 
Acked-by: Stephen Warren 
Signed-off-by: Mike Turquette

clk: tegra: Add new fields and PLL types for Tegra114

2013-04-04T22:10:52+00:00

Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.

Signed-off-by: Peter De Schrijver 
Acked-by: Mike Turquette 
Signed-off-by: Stephen Warren

clk: tegra: move from a lock bit idx to a lock mask

2013-04-04T22:10:49+00:00

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.

Signed-off-by: Peter De Schrijver 
Acked-by: Mike Turquette 
Signed-off-by: Stephen Warren

clk: tegra: Add PLL post divider table

2013-04-04T22:10:45+00:00

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver 
Acked-by: Mike Turquette 
Signed-off-by: Stephen Warren

clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

2013-04-04T22:10:42+00:00

Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.

Signed-off-by: Peter De Schrijver 
Acked-by: Mike Turquette 
Signed-off-by: Stephen Warren

clk: tegra: Add TEGRA_PLL_BYPASS flag

2013-04-04T22:10:38+00:00

Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.

Signed-off-by: Peter De Schrijver 
Acked-by: Mike Turquette 
Signed-off-by: Stephen Warren

clk: tegra: Refactor PLL programming code

2013-04-04T22:10:33+00:00

Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.

The following changes were done:

* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
  by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()

Signed-off-by: Peter De Schrijver 
Acked-by: Mike Turquette 
Signed-off-by: Stephen Warren