<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/clk/tegra, branch v4.4.73</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next</title>
<updated>2015-10-20T15:49:11+00:00</updated>
<author>
<name>Michael Turquette</name>
<email>mturquette@baylibre.com</email>
</author>
<published>2015-10-20T15:49:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=eae14465de250be75021659789f138a70a553ac5'/>
<id>eae14465de250be75021659789f138a70a553ac5</id>
<content type='text'>
clk: tegra: Changes for v4.4-rc1

This contains a patch that allows the DFLL to use clock rates higher
than 2^31-1 Hz by using the -&gt;determine_rate() operation instead of the
-&gt;round_rate() operation. Other than that there's a couple of cleanups
in preparation for Tegra210 support.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
clk: tegra: Changes for v4.4-rc1

This contains a patch that allows the DFLL to use clock rates higher
than 2^31-1 Hz by using the -&gt;determine_rate() operation instead of the
-&gt;round_rate() operation. Other than that there's a couple of cleanups
in preparation for Tegra210 support.
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: Modify tegra_audio_clk_init to accept more plls</title>
<updated>2015-10-20T11:56:55+00:00</updated>
<author>
<name>Rhyland Klein</name>
<email>rklein@nvidia.com</email>
</author>
<published>2015-06-18T21:28:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=88d909bedf4df7285d6e8d8730425df0d163512e'/>
<id>88d909bedf4df7285d6e8d8730425df0d163512e</id>
<content type='text'>
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.

Reviewed-by: Benson Leung &lt;bleung@chromium.org&gt;
Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.

Reviewed-by: Benson Leung &lt;bleung@chromium.org&gt;
Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: Update struct tegra_clk_pll_params kerneldoc</title>
<updated>2015-10-20T11:56:55+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-06-18T21:28:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=db592c4e2b6010069efc983ba3a35f0850844132'/>
<id>db592c4e2b6010069efc983ba3a35f0850844132</id>
<content type='text'>
Benson Leung pointed out that the kerneldoc for this structure has
become stale. Update the field descriptions to match the structure
content.

Reported-by: Benson Leung &lt;bleung@chromium.org&gt;
Acked-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Benson Leung &lt;bleung@chromium.org&gt;
Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Benson Leung pointed out that the kerneldoc for this structure has
become stale. Update the field descriptions to match the structure
content.

Reported-by: Benson Leung &lt;bleung@chromium.org&gt;
Acked-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Benson Leung &lt;bleung@chromium.org&gt;
Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: Fix comments for structure definitions</title>
<updated>2015-10-20T11:56:55+00:00</updated>
<author>
<name>Rhyland Klein</name>
<email>rklein@nvidia.com</email>
</author>
<published>2015-04-13T16:38:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=fdc1feadc0ac19b056482023c82ba624ff704495'/>
<id>fdc1feadc0ac19b056482023c82ba624ff704495</id>
<content type='text'>
Some fields moved from the tegra_clk_pll struct to the tegra_pll_params
struct. Update the struct comments to reflect where the fields really
are.

Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Reviewed-by: Benson Leung &lt;bleung@chromium.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some fields moved from the tegra_clk_pll struct to the tegra_pll_params
struct. Update the struct comments to reflect where the fields really
are.

Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Reviewed-by: Benson Leung &lt;bleung@chromium.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: dfll: Monitor code is DEBUG_FS only</title>
<updated>2015-10-20T11:56:54+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-08-14T10:40:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4182b8d454331c5ca85b57c0a7357073d96b170f'/>
<id>4182b8d454331c5ca85b57c0a7357073d96b170f</id>
<content type='text'>
The monitor code is used with DEBUG_FS only, so move it into the
corresponding #ifdef block to avoid potential compiler warnings.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The monitor code is used with DEBUG_FS only, so move it into the
corresponding #ifdef block to avoid potential compiler warnings.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: delete unneeded of_node_put</title>
<updated>2015-10-12T18:52:48+00:00</updated>
<author>
<name>Julia Lawall</name>
<email>Julia.Lawall@lip6.fr</email>
</author>
<published>2015-10-09T17:47:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4e4f485c89c95c317fadf9faf76d703f0cc7a34d'/>
<id>4e4f485c89c95c317fadf9faf76d703f0cc7a34d</id>
<content type='text'>
for_each_child_of_node performs an of_node_put on each iteration, so
putting an of_node_put before a continue results in a double put.

The semantic match that finds this problem is as follows
(http://coccinelle.lip6.fr):

// &lt;smpl&gt;
@@
expression root,e;
local idexpression child;
iterator name for_each_child_of_node;
@@

 for_each_child_of_node(root, child) {
   ... when != of_node_get(child)
*  of_node_put(child);
   ...
*  continue;
}
// &lt;/smpl&gt;

Signed-off-by: Julia Lawall &lt;Julia.Lawall@lip6.fr&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
for_each_child_of_node performs an of_node_put on each iteration, so
putting an of_node_put before a continue results in a double put.

The semantic match that finds this problem is as follows
(http://coccinelle.lip6.fr):

// &lt;smpl&gt;
@@
expression root,e;
local idexpression child;
iterator name for_each_child_of_node;
@@

 for_each_child_of_node(root, child) {
   ... when != of_node_get(child)
*  of_node_put(child);
   ...
*  continue;
}
// &lt;/smpl&gt;

Signed-off-by: Julia Lawall &lt;Julia.Lawall@lip6.fr&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: dfll: Properly protect OPP list</title>
<updated>2015-09-16T22:16:03+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-09-10T13:55:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=e1595d89ae8180e0d3815cc75336ac3484de0aa0'/>
<id>e1595d89ae8180e0d3815cc75336ac3484de0aa0</id>
<content type='text'>
The OPP list needs to be protected against concurrent accesses. Using
simple RCU read locks does the trick and gets rid of the following
lockdep warning:

	===============================
	[ INFO: suspicious RCU usage. ]
	4.2.0-next-20150908 #1 Not tainted
	-------------------------------
	drivers/base/power/opp.c:460 Missing rcu_read_lock() or dev_opp_list_lock protection!

	other info that might help us debug this:

	rcu_scheduler_active = 1, debug_locks = 0
	4 locks held by kworker/u8:0/6:
	 #0:  ("%s""deferwq"){++++.+}, at: [&lt;c0040d8c&gt;] process_one_work+0x118/0x4bc
	 #1:  (deferred_probe_work){+.+.+.}, at: [&lt;c0040d8c&gt;] process_one_work+0x118/0x4bc
	 #2:  (&amp;dev-&gt;mutex){......}, at: [&lt;c03b8194&gt;] __device_attach+0x20/0x118
	 #3:  (prepare_lock){+.+...}, at: [&lt;c054bc08&gt;] clk_prepare_lock+0x10/0xf8

	stack backtrace:
	CPU: 2 PID: 6 Comm: kworker/u8:0 Not tainted 4.2.0-next-20150908 #1
	Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
	Workqueue: deferwq deferred_probe_work_func
	[&lt;c001802c&gt;] (unwind_backtrace) from [&lt;c00135a4&gt;] (show_stack+0x10/0x14)
	[&lt;c00135a4&gt;] (show_stack) from [&lt;c02a8418&gt;] (dump_stack+0x94/0xd4)
	[&lt;c02a8418&gt;] (dump_stack) from [&lt;c03c6f6c&gt;] (dev_pm_opp_find_freq_ceil+0x108/0x114)
	[&lt;c03c6f6c&gt;] (dev_pm_opp_find_freq_ceil) from [&lt;c0551a3c&gt;] (dfll_calculate_rate_request+0xb8/0x170)
	[&lt;c0551a3c&gt;] (dfll_calculate_rate_request) from [&lt;c0551b10&gt;] (dfll_clk_round_rate+0x1c/0x2c)
	[&lt;c0551b10&gt;] (dfll_clk_round_rate) from [&lt;c054de2c&gt;] (clk_calc_new_rates+0x1b8/0x228)
	[&lt;c054de2c&gt;] (clk_calc_new_rates) from [&lt;c054e44c&gt;] (clk_core_set_rate_nolock+0x44/0xac)
	[&lt;c054e44c&gt;] (clk_core_set_rate_nolock) from [&lt;c054e4d8&gt;] (clk_set_rate+0x24/0x34)
	[&lt;c054e4d8&gt;] (clk_set_rate) from [&lt;c0512460&gt;] (tegra124_cpufreq_probe+0x120/0x230)
	[&lt;c0512460&gt;] (tegra124_cpufreq_probe) from [&lt;c03b9cbc&gt;] (platform_drv_probe+0x44/0xac)
	[&lt;c03b9cbc&gt;] (platform_drv_probe) from [&lt;c03b84c8&gt;] (driver_probe_device+0x218/0x304)
	[&lt;c03b84c8&gt;] (driver_probe_device) from [&lt;c03b69b0&gt;] (bus_for_each_drv+0x60/0x94)
	[&lt;c03b69b0&gt;] (bus_for_each_drv) from [&lt;c03b8228&gt;] (__device_attach+0xb4/0x118)
	ata1: SATA link down (SStatus 0 SControl 300)
	[&lt;c03b8228&gt;] (__device_attach) from [&lt;c03b77c8&gt;] (bus_probe_device+0x88/0x90)
	[&lt;c03b77c8&gt;] (bus_probe_device) from [&lt;c03b7be8&gt;] (deferred_probe_work_func+0x58/0x8c)
	[&lt;c03b7be8&gt;] (deferred_probe_work_func) from [&lt;c0040dfc&gt;] (process_one_work+0x188/0x4bc)
	[&lt;c0040dfc&gt;] (process_one_work) from [&lt;c004117c&gt;] (worker_thread+0x4c/0x4f4)
	[&lt;c004117c&gt;] (worker_thread) from [&lt;c0047230&gt;] (kthread+0xe4/0xf8)
	[&lt;c0047230&gt;] (kthread) from [&lt;c000f7d0&gt;] (ret_from_fork+0x14/0x24)

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Fixes: c4fe70ada40f ("clk: tegra: Add closed loop support for the DFLL")
[vince.h@nvidia.com: Unlock rcu on error path]
Signed-off-by: Vince Hsu &lt;vince.h@nvidia.com&gt;
[sboyd@codeaurora.org: Dropped second hunk that nested the rcu
read lock unnecessarily]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The OPP list needs to be protected against concurrent accesses. Using
simple RCU read locks does the trick and gets rid of the following
lockdep warning:

	===============================
	[ INFO: suspicious RCU usage. ]
	4.2.0-next-20150908 #1 Not tainted
	-------------------------------
	drivers/base/power/opp.c:460 Missing rcu_read_lock() or dev_opp_list_lock protection!

	other info that might help us debug this:

	rcu_scheduler_active = 1, debug_locks = 0
	4 locks held by kworker/u8:0/6:
	 #0:  ("%s""deferwq"){++++.+}, at: [&lt;c0040d8c&gt;] process_one_work+0x118/0x4bc
	 #1:  (deferred_probe_work){+.+.+.}, at: [&lt;c0040d8c&gt;] process_one_work+0x118/0x4bc
	 #2:  (&amp;dev-&gt;mutex){......}, at: [&lt;c03b8194&gt;] __device_attach+0x20/0x118
	 #3:  (prepare_lock){+.+...}, at: [&lt;c054bc08&gt;] clk_prepare_lock+0x10/0xf8

	stack backtrace:
	CPU: 2 PID: 6 Comm: kworker/u8:0 Not tainted 4.2.0-next-20150908 #1
	Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
	Workqueue: deferwq deferred_probe_work_func
	[&lt;c001802c&gt;] (unwind_backtrace) from [&lt;c00135a4&gt;] (show_stack+0x10/0x14)
	[&lt;c00135a4&gt;] (show_stack) from [&lt;c02a8418&gt;] (dump_stack+0x94/0xd4)
	[&lt;c02a8418&gt;] (dump_stack) from [&lt;c03c6f6c&gt;] (dev_pm_opp_find_freq_ceil+0x108/0x114)
	[&lt;c03c6f6c&gt;] (dev_pm_opp_find_freq_ceil) from [&lt;c0551a3c&gt;] (dfll_calculate_rate_request+0xb8/0x170)
	[&lt;c0551a3c&gt;] (dfll_calculate_rate_request) from [&lt;c0551b10&gt;] (dfll_clk_round_rate+0x1c/0x2c)
	[&lt;c0551b10&gt;] (dfll_clk_round_rate) from [&lt;c054de2c&gt;] (clk_calc_new_rates+0x1b8/0x228)
	[&lt;c054de2c&gt;] (clk_calc_new_rates) from [&lt;c054e44c&gt;] (clk_core_set_rate_nolock+0x44/0xac)
	[&lt;c054e44c&gt;] (clk_core_set_rate_nolock) from [&lt;c054e4d8&gt;] (clk_set_rate+0x24/0x34)
	[&lt;c054e4d8&gt;] (clk_set_rate) from [&lt;c0512460&gt;] (tegra124_cpufreq_probe+0x120/0x230)
	[&lt;c0512460&gt;] (tegra124_cpufreq_probe) from [&lt;c03b9cbc&gt;] (platform_drv_probe+0x44/0xac)
	[&lt;c03b9cbc&gt;] (platform_drv_probe) from [&lt;c03b84c8&gt;] (driver_probe_device+0x218/0x304)
	[&lt;c03b84c8&gt;] (driver_probe_device) from [&lt;c03b69b0&gt;] (bus_for_each_drv+0x60/0x94)
	[&lt;c03b69b0&gt;] (bus_for_each_drv) from [&lt;c03b8228&gt;] (__device_attach+0xb4/0x118)
	ata1: SATA link down (SStatus 0 SControl 300)
	[&lt;c03b8228&gt;] (__device_attach) from [&lt;c03b77c8&gt;] (bus_probe_device+0x88/0x90)
	[&lt;c03b77c8&gt;] (bus_probe_device) from [&lt;c03b7be8&gt;] (deferred_probe_work_func+0x58/0x8c)
	[&lt;c03b7be8&gt;] (deferred_probe_work_func) from [&lt;c0040dfc&gt;] (process_one_work+0x188/0x4bc)
	[&lt;c0040dfc&gt;] (process_one_work) from [&lt;c004117c&gt;] (worker_thread+0x4c/0x4f4)
	[&lt;c004117c&gt;] (worker_thread) from [&lt;c0047230&gt;] (kthread+0xe4/0xf8)
	[&lt;c0047230&gt;] (kthread) from [&lt;c000f7d0&gt;] (ret_from_fork+0x14/0x24)

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Fixes: c4fe70ada40f ("clk: tegra: Add closed loop support for the DFLL")
[vince.h@nvidia.com: Unlock rcu on error path]
Signed-off-by: Vince Hsu &lt;vince.h@nvidia.com&gt;
[sboyd@codeaurora.org: Dropped second hunk that nested the rcu
read lock unnecessarily]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: Unlock top rates for Tegra124 DFLL clock</title>
<updated>2015-09-15T10:54:39+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mikko.perttunen@kapsi.fi</email>
</author>
<published>2015-09-15T09:55:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=10d9be6ebe9199feb7680433a24b564a31a8f9b1'/>
<id>10d9be6ebe9199feb7680433a24b564a31a8f9b1</id>
<content type='text'>
The new determine_rate prototype allows for clock rates exceeding
2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate
instead of round_rate and unlock the top rates supported by the
Tegra124.

Signed-off-by: Mikko Perttunen &lt;mikko.perttunen@kapsi.fi&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The new determine_rate prototype allows for clock rates exceeding
2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate
instead of round_rate and unlock the top rates supported by the
Tegra124.

Signed-off-by: Mikko Perttunen &lt;mikko.perttunen@kapsi.fi&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: tegra: Fix some static checker problems</title>
<updated>2015-08-25T23:03:42+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2015-08-25T23:02:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c5a132a84a692f8d81f3b6959b98bcd959659457'/>
<id>c5a132a84a692f8d81f3b6959b98bcd959659457</id>
<content type='text'>
The latest Tegra clk pull had some problems. Fix them.

drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static?
drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting
drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td-&gt;i2c_lut[0]' is never less than zero.

Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The latest Tegra clk pull had some problems. Fix them.

drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static?
drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting
drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td-&gt;i2c_lut[0]' is never less than zero.

Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next</title>
<updated>2015-08-25T22:55:28+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2015-08-25T22:55:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a7c602bf42f943e717eed92165ebfa6dbaba3029'/>
<id>a7c602bf42f943e717eed92165ebfa6dbaba3029</id>
<content type='text'>
clk: tegra: Changes for v4.3-rc1

This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
clk: tegra: Changes for v4.3-rc1

This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
</pre>
</div>
</content>
</entry>
</feed>
