linux-toradex.git/drivers/clk/ti/fapll.c, branch v4.2.6

clk: ti: Silence sparse warnings

2015-05-15T00:11:26+00:00

drivers/clk/ti/clk.c:125:31: warning: incorrect type in return expression (different address spaces)
drivers/clk/ti/clk.c:125:31:    expected void [noderef] *
drivers/clk/ti/clk.c:125:31:    got void *
drivers/clk/ti/clk.c:132:31: warning: incorrect type in return expression (different address spaces)
drivers/clk/ti/clk.c:132:31:    expected void [noderef] *
drivers/clk/ti/clk.c:132:31:    got void *
drivers/clk/ti/dpll.c:180:14: warning: symbol '_get_reg' was not declared. Should it be static?
drivers/clk/ti/fapll.c:624:32: warning: Using plain integer as NULL pointer
drivers/clk/ti/fapll.c:625:31: warning: Using plain integer as NULL pointer
drivers/clk/ti/fapll.c:630:40: warning: Using plain integer as NULL pointer
drivers/clk/ti/clk-dra7-atl.c:158:22: warning: symbol 'atl_clk_ops' was not declared. Should it be static?
drivers/clk/ti/clk-dra7-atl.c:170:39: warning: Using plain integer as NULL pointer

Acked-by: Peter Ujfalusi 
Acked-by: Tero Kristo 
Signed-off-by: Stephen Boyd

Merge branch 'for-4.1-clk-ti' of github.com:t-kristo/linux-pm into clk-next

2015-03-24T23:47:43+00:00

clk: ti: Implement FAPLL set_rate for the PLL

2015-03-24T18:26:14+00:00

Since we have a fractional divider for the synthesizer, just implement
a simple multiply logic for the PLL.

It seems the PLL divider needs to have also the multiplier set for the PLL
to lock. At least I have not yet figured out if divided rates are doable.

So let's just ignore the PLL divider for now as the synthesizer has both
integer and fractional dividers so we don't even need to use the PLL
divider for the rates we know work with PLL locking.

Cc: Brian Hutchinson 
Cc: Matthijs van Duin 
Cc: Tero Kristo 
Signed-off-by: Tony Lindgren 
Signed-off-by: Tero Kristo

clk: ti: Implement FAPLL set_rate for the synthesizer

2015-03-24T18:26:05+00:00

We can pretty much get any rate out of the FAPLL because of the fractional
divider. Let's first try just adjusting the post divider, and if that is
not enough, then reprogram both the fractional divider and the post divider.

Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8.

Cc: Brian Hutchinson 
Cc: Matthijs van Duin 
Cc: Tero Kristo 
Signed-off-by: Tony Lindgren 
Signed-off-by: Tero Kristo

clk: ti: Fix FAPLL recalc_rate for rounding errors

2015-03-24T18:26:05+00:00

We need to round the calculated value to have it match the requested rate.

While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we
will need it in later patches for set_rate.

And let's remove two unused includes.

Cc: Brian Hutchinson 
Cc: Matthijs van Duin 
Cc: Tero Kristo 
Signed-off-by: Tony Lindgren 
Signed-off-by: Tero Kristo

clk: ti: Fix FAPLL parent enable bit handling

2015-02-25T20:06:29+00:00

Commit 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x")
added basic support for the FAPLL on dm818x, but has a bug for the
parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3)
but the code is doing a shift on it.

This means the parent PLL won't get disabled even if all it's child
synthesizers are disabled.

Reported-by: Dan Carpenter 
Cc: Brian Hutchinson 
Signed-off-by: Tony Lindgren 
Signed-off-by: Michael Turquette

clk: ti: Add support for FAPLL on dm816x

2015-01-20T18:09:07+00:00

On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson 
Cc: Paul Walmsley 
Cc: Tero Kristo 
Signed-off-by: Tony Lindgren 
Signed-off-by: Michael Turquette