linux-toradex.git/drivers/clk/uniphier, branch v5.8-rc2

clk: uniphier: Add SCSSI clock gate for each channel

2020-01-05T07:14:22+00:00

SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.

Fixes: ff388ee36516 ("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi 
Acked-by: Masahiro Yamada 
Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd

drivers/clk: convert VL struct to struct_size

2019-11-08T16:36:12+00:00

There are a few manually-calculated variable-length struct allocations
left, this converts them to use struct_size. Found with the following
git grep command

	git grep -A1 'kzalloc.*sizeof[^_].*+'

Signed-off-by: Stephen Kitt 
Link: https://lkml.kernel.org/r/20190927185110.29897-1-steve@sk2.org
Acked-by: Gustavo A. R. Silva 
[sboyd@kernel.org: Add grep command]
Signed-off-by: Stephen Boyd

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30T18:26:37+00:00

Based on 3 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version [author] [kishon] [vijay] [abraham]
  [i] [kishon]@[ti] [com] this program is distributed in the hope that
  it will be useful but without any warranty without even the implied
  warranty of merchantability or fitness for a particular purpose see
  the gnu general public license for more details

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version [author] [graeme] [gregory]
  [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i]
  [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema]
  [hk] [hemahk]@[ti] [com] this program is distributed in the hope
  that it will be useful but without any warranty without even the
  implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 1105 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Reviewed-by: Richard Fontana 
Reviewed-by: Kate Stewart 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de
Signed-off-by: Greg Kroah-Hartman

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21T08:50:46+00:00

Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner 
Signed-off-by: Greg Kroah-Hartman

clk: uniphier: Fix update register for CPU-gear

2019-02-21T21:50:23+00:00

Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update
the CPU-gear value.

Fixes: d08f1f0d596c ("clk: uniphier: add CPU-gear change (cpufreq) support")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Kunihiko Hayashi 
Acked-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: uniphier: add clock frequency support for SPI

2018-07-25T23:26:18+00:00

Add clock control for SPI controller on UniPhier SoCs.

Signed-off-by: Kunihiko Hayashi 
Signed-off-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: uniphier: add more USB3 PHY clocks

2018-07-25T22:45:32+00:00

Add USB3 PHY clocks where missing.  Use fixed-factor clocks for those
without gating.

For clarification, prefix clock names with 'ss' or 'hs'.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: uniphier: add NAND 200MHz clock

2018-07-25T22:45:25+00:00

The Denali NAND controller IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

Currently, only the first one (50MHz) is provided.  The rest of the
two clock ports must be connected to the 200MHz clock line.  Add this.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: uniphier: add LD11/LD20 stream demux system clock

2018-05-15T21:15:43+00:00

Add clock for MPEG2 transport stream I/O and demux system (HSC) on
UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki 
Acked-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd

clk: uniphier: add additional ethernet clock lines for Pro4

2018-04-05T22:03:51+00:00

Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
and these are mandatory to activate the ethernet controller. This adds
support for the clock lines.

Signed-off-by: Kunihiko Hayashi 
Acked-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd