linux-toradex.git/drivers/clk/zte, branch v5.0

clk: move clock common macros out from vendor directories

2017-12-21T23:00:38+00:00

These macros are used by more than one SoC vendor platforms, avoid to
have many copies of these code, this patch moves them to the common
header file which every clock drivers can access to.

Signed-off-by: Chunyan Zhang 
Signed-off-by: Stephen Boyd

clk: zte: constify clk_div_table

2017-08-31T05:30:30+00:00

clk_div_table are not supposed to change at runtime. All functions
working with clk_div_table provided by  work
with const clk_div_table. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd

clk: zx296718: export I2S mux clocks

2017-06-20T02:02:42+00:00

Export I2S mux clocks, so that device tree can refer to them for setting
a better parent clock for I2S work clock.

Signed-off-by: Shawn Guo 
Signed-off-by: Stephen Boyd

clk: zte: Mark pll config tables as const

2017-04-12T16:51:34+00:00

These should be const.

Cc: Shawn Guo 
Cc: Jun Nie 
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: zte: add pll_vga clock for zx296718

2017-04-12T16:51:33+00:00

It adds zx296718 pll_vga clock for VGA support, so that VGA device can
get required pixel rate from clock driver for different display mode.

Signed-off-by: Shawn Guo 
Reviewed-by: Jun Nie 
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: zte: pd_bit is not 0 on zx296718

2017-04-12T16:51:31+00:00

The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field.  The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.

Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.

Signed-off-by: Shawn Guo 
Reviewed-by: Jun Nie 
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks

2017-04-12T16:51:29+00:00

To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.

While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.

Signed-off-by: Shawn Guo 
Reviewed-by: Jun Nie 
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: zte: add i2s clocks for zx296718

2017-02-10T17:17:38+00:00

The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.

Signed-off-by: Baoyou Xie 
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd

clk: zte: add audio clocks for zx296718

2017-01-10T00:06:43+00:00

The audio related clock support is missing from the existing zx296718
clock driver.  Let's add it, so that the upstream ZX SPDIF driver can
work for HDMI audio support.

Signed-off-by: Jun Nie 
Signed-off-by: Shawn Guo 
[sboyd@codeaurora.org: Staticize some more structures]
Signed-off-by: Stephen Boyd

clk: zx296718: do not panic on failure

2017-01-10T00:06:42+00:00

Instead of using panic, we should give an error message and return error
code when of_clk_add_hw_provider() call fails.

Since we have error prompt for failures, the "init over" pr_info output
isn't really necessary but becomes a debug noise.  So let's clean it up
along the way.

Signed-off-by: Shawn Guo 
Signed-off-by: Stephen Boyd