linux-toradex.git/drivers/clk/zynq, branch v3.14.33

clk/zynq/clkc: Add 'fclk-enable' feature

2013-12-20T12:23:55+00:00

In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT description to accomodate such use
cases. It's value is a bitmask, where a set bit results in enabling
the corresponding FCLK through the clkc.

FPGA clocks are handled following the rules below:

If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
Linux. Drivers can enable and control it through the CCF as usual.

If an FCLK is enabled by bootloaders AND the corresponding bit in the
'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
resulting in an off by one reference count for that clock. Ensuring it
will always be running.

Signed-off-by: Soren Brinkmann 
Acked-by: Michal Simek 
Signed-off-by: Michal Simek

clk/zynq: Fix possible memory leak

2013-10-08T05:43:27+00:00

The zynq_clk_register_fclk function can leak memory (fclk_lock) when unable
to alloc memory for fclk_gate_lock

Signed-off-by: Felipe Pena 
Acked-by: Sören Brinkmann 
Signed-off-by: Mike Turquette

Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

2013-09-09T22:49:04+00:00

Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...

Merge tag 'zynq-clk-for-3.12' of git://git.xilinx.com/linux-xlnx into clk-next

2013-08-20T21:58:48+00:00

arm: Xilinx Zynq clock changes for v3.12

Just small two changes where the first fixes
documentation and the second improves
code readability.

clk/zynq/pll: Use #defines for fbdiv min/max values

2013-08-20T05:54:41+00:00

Use more descriptive #defines for the minimum and maximum PLL
feedback divider.

Signed-off-by: Soren Brinkmann 
Signed-off-by: Michal Simek

clk/zynq/pll: Fix documentation for PLL register function

2013-08-20T05:54:40+00:00

Signed-off-by: Soren Brinkmann 
Signed-off-by: Michal Simek

clk: add CLK_SET_RATE_NO_REPARENT flag

2013-08-19T19:27:17+00:00

Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.

Signed-off-by: James Hogan 
Reviewed-by: Stephen Boyd 
Cc: Mike Turquette 
Cc: Russell King 
Cc: Sascha Hauer 
Cc: Stephen Warren 
Cc: Viresh Kumar 
Cc: Kukjin Kim 
Cc: Haojian Zhuang 
Cc: Chao Xie 
Cc: Arnd Bergmann 
Cc: "Emilio López" 
Cc: Gregory CLEMENT 
Cc: Maxime Ripard 
Cc: Prashant Gaikwad 
Cc: Thierry Reding 
Cc: Peter De Schrijver 
Cc: Pawel Moll 
Cc: Catalin Marinas 
Cc: Andrew Chew 
Cc: Doug Anderson 
Cc: Heiko Stuebner 
Cc: Paul Walmsley 
Cc: Sylwester Nawrocki 
Cc: Thomas Abraham 
Cc: Tomasz Figa 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang 
Acked-by: Stephen Warren  [tegra]
Acked-by: Maxime Ripard  [sunxi]
Acked-by: Sören Brinkmann  [Zynq]
Signed-off-by: Mike Turquette

clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes

2013-08-13T17:01:55+00:00

Zynq's Ethernet clocks are created by the following hierarchy:
	mux0 ---> div0 ---> div1 ---> mux1 ---> gate
Rate change requests on the gate have to propagate all the way up to
div0 to properly leverage all dividers. Mux1 was missing the
CLK_SET_RATE_PARENT flag, which is required to achieve this.

This does not fix a specific regression but the clock driver was merged
for 3.11-rc1, so best to fix the known bugs before the release.

Signed-off-by: Soren Brinkmann 
Signed-off-by: Michal Simek 
Signed-off-by: Mike Turquette 
[mturquette@linaro.org: added to changelog]

clk/zynq/clkc: Add dedicated spinlock for the SWDT

2013-08-13T17:01:55+00:00

The clk_mux for the system watchdog timer reused the register lock
dedicated to the Ethernet module - for no apparent reason.
Add a lock dedicated to the SWDT's clock register to remove this
wrong dependency.

This does not fix a specific regression but the clock driver was merged
for 3.11-rc1, so best to fix the known bugs before the release.

Signed-off-by: Soren Brinkmann 
Signed-off-by: Michal Simek 
Signed-off-by: Mike Turquette 
[mturquette@linaro.org: added to changelog]

arm: zynq: Migrate platform to clock controller

2013-05-27T07:21:22+00:00

Migrate the Zynq platform and its drivers to use the new clock
controller driver.

Signed-off-by: Soren Brinkmann 
Cc: John Stultz 
Cc: Thomas Gleixner 
Cc: Greg Kroah-Hartman 
Cc: Jiri Slaby 
Cc: linux-serial@vger.kernel.org
Signed-off-by: Michal Simek 
Acked-by: Mike Turquette