linux-toradex.git/drivers/clk, branch v3.14.46

clk: qcom: fix RCG M/N counter configuration

2015-05-06T19:59:18+00:00

commit 0b21503dbbfa669dbd847b33578d4041513cddb2 upstream.

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja 
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: tegra: Register the proper number of resets

2015-05-06T19:59:18+00:00

commit 5e43e259171e1eee8bc074d9c44be434e685087b upstream.

The number of resets controls is 32 times the number of peripheral
register banks rather than 32 times the number of clocks. This reduces
(drastically) the number of reset controls registered from 10080 (315
clocks * 32) to 224 (6 peripheral register banks * 32).

This also fixes a potential crash because trying to use any of the
excess reset controls (224-10079) would have caused accesses beyond
the array bounds of the peripheral register banks definition array.

Cc: Peter De Schrijver 
Cc: Prashant Gaikwad 
Fixes: 6d5b988e7dc5 ("clk: tegra: implement a reset driver")
Signed-off-by: Thierry Reding 
Signed-off-by: Greg Kroah-Hartman

clk-gate: fix bit # check in clk_register_gate()

2015-03-18T12:31:34+00:00

commit 2e9dcdae4068460c45a308dd891be5248260251c upstream.

In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 045779942c04 ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi: Support factor clocks with N factor starting not from 0

2015-03-18T12:31:32+00:00

commit 9a5e6c7eb5ccbb5f0d3a1dffce135f0a727f40e1 upstream.

The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.

This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

sunxi: clk: Set sun6i-pll1 n_start = 1

2015-03-18T12:31:32+00:00

commit 76820fcf7aa5a418b69cb7bed31b62d1feb1d6ad upstream.

For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as
it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set
for sun6i pll6, but was missing for pll1, this commit fixes this.

Cc: Chen-Yu Tsai 
Signed-off-by: Hans de Goede 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: zynq: Force CPU_2X clock to be ungated

2015-03-18T12:31:32+00:00

commit 3dccfecdb867fe35b305a4e493ef5652b7d9d4cb upstream.

The CPU_2X clock does not have a classical in-kernel user, but is,
amongst other things, required for OCM and debug access. Make sure this
clock is not mistakenly disabled during boot up by enabling it in the
platform's clock driver.

Fixes: 0ee52b157b8e 'clk: zynq: Add clock controller driver'
Signed-off-by: Soren Brinkmann 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: Don't try to use a struct clk* after it could have been freed

2015-01-27T16:18:55+00:00

commit 10cdfe54dab034311c8e2fad9ba2dffbe616caa9 upstream.

As __clk_release could call kfree on clk and then we wouldn't have a safe way
of getting the module that owns the clock.

Signed-off-by: Tomeu Vizoso 
Fixes: fcb0ee6a3d33 ("clk: Implement clk_unregister")
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: Fix double add of syscore ops after driver rebind

2015-01-27T16:18:55+00:00

commit c31844ffdbd4e73a16c66e9d7df8ec290ab4b159 upstream.

During driver unbind the syscore ops were not unregistered which lead to
double add on syscore list:

$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind
$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind
[ 1463.044061] ------------[ cut here ]------------
[ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0()
[ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84.
[ 1463.061625] Modules linked in:
[ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G        W      3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022
[ 1463.075338] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[ 1463.083046] [] (show_stack) from [] (dump_stack+0x70/0xbc)
[ 1463.090236] [] (dump_stack) from [] (warn_slowpath_common+0x74/0xb0)
[ 1463.098295] [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
[ 1463.106962] [] (warn_slowpath_fmt) from [] (__list_add+0x8c/0xc0)
[ 1463.114760] [] (__list_add) from [] (register_syscore_ops+0x30/0x3c)
[ 1463.122819] [] (register_syscore_ops) from [] (exynos_audss_clk_probe+0x36c/0x460)
[ 1463.132091] [] (exynos_audss_clk_probe) from [] (platform_drv_probe+0x48/0xa4)
[ 1463.141013] [] (platform_drv_probe) from [] (driver_probe_device+0x13c/0x37c)
[ 1463.149852] [] (driver_probe_device) from [] (bind_store+0x90/0xe0)
[ 1463.157822] [] (bind_store) from [] (drv_attr_store+0x20/0x2c)
[ 1463.165363] [] (drv_attr_store) from [] (sysfs_kf_write+0x4c/0x50)
[ 1463.173252] [] (sysfs_kf_write) from [] (kernfs_fop_write+0xbc/0x198)
[ 1463.181395] [] (kernfs_fop_write) from [] (vfs_write+0xa0/0x1a8)
[ 1463.189104] [] (vfs_write) from [] (SyS_write+0x40/0x8c)
[ 1463.196122] [] (SyS_write) from [] (ret_fast_syscall+0x0/0x48)
[ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]---
[ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed

Signed-off-by: Krzysztof Kozlowski 
Fixes: 1241ef94ccc3 ("clk: samsung: register audio subsystem clocks using common clock framework")
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: mdp_lut_clk is a child of mdp_src

2014-10-05T21:52:24+00:00

commit f87dfcabc6f173cc811d185d33327f50a8c88399 upstream.

The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the
child of the mdp_src clock. Fix it.

Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix MN frequency tables, parent map, and jpegd

2014-10-05T21:52:24+00:00

commit ff20783f7b9f35b29e768d8ecc7076c1ca1a60ca upstream.

Clocks that don't have a pre-divider don't list any pre-divider
in their frequency tables, but their tables are initialized using
aggregate initializers. Use tagged initializers so we properly
assign the m and n values for each frequency. Furthermore, the
mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second
element to pll2 instead of pll8, causing the clock driver to
recalculate the wrong rate for any clocks using this array along
with a rate that uses pll2. Plus the .num_parents field is 3
instead of 4 so you can't even switch the parent to pll3. Finally
I noticed that the jpegd clock improperly indicates that the
pre-divider width is only 2, when it's actually 4 bits wide.

Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Tested-by: Rob Clark 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman