linux-toradex.git/drivers/clk, branch v3.18.23

clk: versatile: off by one in clk_sp810_timerclken_of_get()

2015-10-28T02:14:38+00:00

[ Upstream commit 3294bee87091be5f179474f6c39d1d87769635e2 ]

The ">" should be ">=" or we end up reading beyond the end of the array.

Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter 
Acked-by: Pawel Moll 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: ti: fix dual-registration of uart4_ick

2015-10-28T02:14:26+00:00

[ Upstream commit 19e79687de22f23bcfb5e79cce3daba20af228d1 ]

On the OMAP AM3517 platform the uart4_ick gets registered
twice, causing any power management to /dev/ttyO3 to fail
when trying to wake the device up.

This solves the following oops:

[] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008
[] PC is at serial_omap_pm+0x48/0x15c
[] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c

Fixes: aafd900cab87 ("CLK: TI: add omap3 clock init file")
Cc: stable@vger.kernel.org
Cc: mturquette@baylibre.com
Cc: sboyd@codeaurora.org
Cc: linux-clk@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-kernel@lists.codethink.co.uk
Signed-off-by: Ben Dooks 
Signed-off-by: Tero Kristo 
Signed-off-by: Sasha Levin

clk: keystone: add support for post divider register for main pll

2015-08-22T18:05:31+00:00

[ Upstream commit 02fdfd708fd252a778709beb6c65d5e7360341ac ]

Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.

Signed-off-by: Murali Karicheri 
Signed-off-by: Michael Turquette 
Signed-off-by: Sasha Levin

clk: at91: fix h32mx prototype inclusion in pmc header

2015-07-01T19:37:14+00:00

[ Upstream commit 28df9c2fb6f896179fcffd5a3f5a86e2d1dff0a5 ]

Trivial fix that prevents to compile this pmc clock driver if h32mx clock is
present but smd clock isn't.

Signed-off-by: Nicolas Ferre 
Signed-off-by: Boris Brezillon 
Acked-by: Alexandre Belloni 
Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock")
Cc:  # 3.18+
Signed-off-by: Sasha Levin

clk: at91: pll: fix input range validity check

2015-07-01T19:36:18+00:00

[ Upstream commit 6c7b03e1aef2e92176435f4fa562cc483422d20f ]

The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.

Cc:  # v3.14+
Signed-off-by: Boris Brezillon 
Reported-by: Jonas Andersson 
Signed-off-by: Sasha Levin

clk: at91: usb: fix determine_rate prototype

2015-05-17T23:12:33+00:00

Commit c67881fc890916206e723329e774391c6ed354ce is a backport of
0b67c43ce36a9964f1d5e3f973ee19eefd3f9f8f upstream commit, fixing a
bug on clk rate change propagation.
But in 4.0 ->determine_rate() prototype has changed, thus introducing
a prototype mismatch when applying it on 3.19.

Signed-off-by: Boris Brezillon 
Signed-off-by: Sasha Levin

clk: qcom: fix RCG M/N counter configuration

2015-05-17T23:12:19+00:00

[ Upstream commit 0b21503dbbfa669dbd847b33578d4041513cddb2 ]

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja 
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd 

Signed-off-by: Sasha Levin

clk: qcom: Fix i2c frequency table

2015-05-17T23:12:19+00:00

[ Upstream commit 0bf0ff82c34da02ee5795101b328225a2d519594 ]

PXO is 25MHz, not 27MHz. Fix the table.

Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"

Signed-off-by: Stephen Boyd 
Reviewed-by: Andy Gross 
Tested-by: Andy Gross 
Signed-off-by: Michael Turquette 
Signed-off-by: Sasha Levin

clk: tegra: Register the proper number of resets

2015-05-17T23:12:18+00:00

[ Upstream commit 5e43e259171e1eee8bc074d9c44be434e685087b ]

The number of resets controls is 32 times the number of peripheral
register banks rather than 32 times the number of clocks. This reduces
(drastically) the number of reset controls registered from 10080 (315
clocks * 32) to 224 (6 peripheral register banks * 32).

This also fixes a potential crash because trying to use any of the
excess reset controls (224-10079) would have caused accesses beyond
the array bounds of the peripheral register banks definition array.

Cc: Peter De Schrijver 
Cc: Prashant Gaikwad 
Fixes: 6d5b988e7dc5 ("clk: tegra: implement a reset driver")
Cc: stable@vger.kernel.org # 3.14+
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC

2015-05-17T23:12:18+00:00

[ Upstream commit 3a9e9cb65be84d6c64fbe9c69a73c15d59f29454 ]

Commit 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK
down feature") enabled ARMCLK down feature on all Exynos4
SoCs.  Unfortunately on Exynos4210 SoC ARMCLK down feature
causes a lockup when ondemand cpufreq governor is used.
Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs.

This patch was tested on:
- Exynos4210 SoC based Trats board
- Exynos4210 SoC based Origen board
- Exynos4412 SoC based Trats2 board
- Exynos4412 SoC based Odroid-U3 board

Cc: Daniel Drake 
Cc: Tomasz Figa 
Cc: Kukjin Kim 
Fixes: 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature")
Cc:  # v3.17+
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Bartlomiej Zolnierkiewicz 
Signed-off-by: Michael Turquette 
Signed-off-by: Sasha Levin