linux-toradex.git/drivers/clk, branch v4.9-rc5

clk: mmp: pxa910: fix return value check in pxa910_clk_init()

2016-11-02T00:41:20+00:00

Fix the retrn value check which testing the wrong variable
in pxa910_clk_init().

Fixes: 2bc61da9f7ff ("clk: mmp: add pxa910 DT support for clock driver")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: mmp: pxa168: fix return value check in pxa168_clk_init()

2016-11-02T00:41:20+00:00

Fix the retrn value check which testing the wrong variable
in pxa168_clk_init().

Fixes: ab08aefcd12d ("clk: mmp: add pxa168 DT support for clock driver")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: mmp: mmp2: fix return value check in mmp2_clk_init()

2016-11-02T00:41:19+00:00

Fix the retrn value check which testing the wrong variable
in mmp2_clk_init().

Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: qoriq: Don't allow CPU clocks higher than starting value

2016-11-02T00:26:15+00:00

The boot-time frequency of a CPU is considered its rated maximum, as we
have no other source of such information.  However, this was previously
only used for chips with 80% restrictions on secondary PLLs.  This
usually wasn't a problem because most chips/configs boot with a divider
of /1, with other dividers being used only for dynamic frequency
reduction.  However, at least one config (LS1021A at less than 1 GHz)
uses a different divider for top speed.  This was causing cpufreq to set
a frequency beyond the chip's rated speed.

This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs,
similar to the existing 80% limit that only applied to some.

Signed-off-by: Scott Wood 
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd

Merge tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

2016-11-02T00:08:13+00:00

Fix return value in error case of new ddrclk type.

* tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: don't return NULL when failing to register ddrclk branch

clk: imx: fix integer overflow in AV PLL round rate

2016-11-02T00:07:54+00:00

Since 'parent_rate * mfn' may overflow 32 bits, the result should be
stored using 64 bits.

The problem was discovered when trying to set the rate of the audio PLL
(pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but
the actual rate returned was 192.000570 MHz. The round rate function should
have been able to return 196.608 MHz, i.e., the desired rate.

Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula")
Cc: Anson Huang 
Signed-off-by: Emil Lundmark 
Reviewed-by: Fabio Estevam 
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd

clk: xgene: Don't call __pa on ioremaped address

2016-10-28T18:03:47+00:00

ioremaped addresses are not linearly mapped so the physical
address can not be figured out via __pa. More generally, there
is no guarantee that backing value of an ioremapped address
is a physical address at all. The value here is only used
for debugging so just drop the call to __pa on the ioremapped
address.

Fixes: 6ae5fd381251 ("clk: xgene: Silence sparse warnings")
Signed-off-by: Laura Abbott 
Acked-by: Loc Ho 
Signed-off-by: Stephen Boyd

clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUT

2016-10-28T00:26:54+00:00

The Exynos PMU node is an interrupt, clock and PMU (Power Management Unit)
controller, and these functionalities are supported by different drivers
that matches the same compatible strings.

Since commit 989eafd0b609 ("clk: core: Avoid double initialization of
clocks") the OF core flags clock controllers registered with the
CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same
compatible string will not be registered.

This prevents the PMU platform device to be created, so the Exynos PMU
driver is never probed. This breaks (among other things) Suspend-to-RAM.

Fix this by changing CLKOUT driver initialization method to
CLK_OF_DECLARE_DRIVER(), which doesn't clear the OF_POPULATED flag, so
later a platform device is created and the Exynos PMU platform driver
can be be probed properly.

Fixes: 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
Signed-off-by: Marek Szyprowski 
Reviewed-by: Javier Martinez Canillas 
Reviewed-by: Chanwoo Choi 
Signed-off-by: Stephen Boyd

clk: at91: Fix a return value in case of error

2016-10-20T23:37:56+00:00

If 'clk_hw_register()' fails, it is likely that we expect to return an
error instead of a valid pointer (which would mean success).

Fix commit f5644f10dcfb ("clk: at91: Migrate to clk_hw based registration
and OF APIs")

Signed-off-by: Christophe JAILLET 
Signed-off-by: Stephen Boyd

clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs

2016-10-19T20:15:05+00:00

I made a mistake as for naming for this block.  The MIO block is not
implemented for these 3 SoCs in the first place.  The current naming
will be a trouble if an SoC with both MIO and SD-ctrl blocks appear
in the future.

This driver has just been merged in the previous merge window.
Rename it before the release.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Stephen Boyd