linux-toradex.git/drivers/clk, branch v4.9.31

clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036

2017-05-14T12:00:19+00:00

commit 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28 upstream.

The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.

Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: Make x86/ conditional on CONFIG_COMMON_CLK

2017-05-14T12:00:17+00:00

commit f35b6542c3ac3f28056d298348a81f7d56d3a041 upstream.

Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK
was not explicit

Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks')
Signed-off-by: Pierre-Louis Bossart 
Acked-by: Andy Shevchenko 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: lpc32xx: add a quirk for PWM and MS clock dividers

2017-04-12T10:41:15+00:00

[ Upstream commit f84d42a9cffc4ecd96f1ce3a038f841782142eb2 ]

In common clock framework CLK_DIVIDER_ONE_BASED or'ed with
CLK_DIVIDER_ALLOW_ZERO flags indicates that
1) a divider clock may be set to zero value,
2) divider's zero value is interpreted as a non-divided clock.

On the LPC32xx platform clock dividers of PWM and memory card clocks
comply with the first condition, but zero value means a gated clock,
thus it may happen that the divider value is not updated when
the clock is enabled and the clock remains gated.

The change adds one-shot quirks, which check for zero value of divider
on initialization and set it to a non-zero value, therefore in runtime
a gate clock will work as expected.

Signed-off-by: Vladimir Zapolskiy 
Reviewed-by: Sylvain Lemieux 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

2017-03-30T07:41:26+00:00

commit ac8616e4c81dded650dfade49a7da283565d37ce upstream.

The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.

This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.

Fixes: 2ab836db5097 ("clk: sunxi-ng: Add M-P factor clock support")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock

2017-03-30T07:41:26+00:00

commit 9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d upstream.

The enable bit offset for the hdmi-ddc module clock is wrong. It is
pointing to the main hdmi module clock enable bit.

Reported-by: Bob Ham 
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: Fix ->fixed_divider of pllh_aux

2017-03-22T11:43:39+00:00

commit f2a46926aba1f0c33944901d2420a6a887455ddc upstream.

There is no fixed divider on pllh_aux.

Signed-off-by: Boris Brezillon 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd 
Cc: Amit Pundir 
Signed-off-by: Greg Kroah-Hartman

ARM: 8631/1: clkdev: Detect errors in clk_hw_register_clkdev() for mass registration

2017-01-15T12:42:57+00:00

commit 9388093db44356af911adf3d355b7544a13a63cd upstream.

Unlike clk_register_clkdev(), clk_hw_register_clkdev() doesn't check for
passed error objects from a previous registration call. Hence the caller
of clk_hw_register_*() has to check for errors before calling
clk_hw_register_clkdev*().

Make clk_hw_register_clkdev() more similar to clk_register_clkdev() by
adding this error check, removing the burden from callers that do mass
registration.

Fixes: e4f1b49bda6d6aa2 ("clkdev: Add clk_hw based registration APIs")
Fixes: 944b9a41e004534f ("clk: ls1x: Migrate to clk_hw based OF and registration APIs")
Fixes: 44ce9a9ae977736f ("MIPS: TXx9: Convert to Common Clock Framework")
Fixes: f48d947a162dfa9d ("clk: clps711x: Migrate to clk_hw based OF and registration APIs")
Fixes: b4626a7f489238a5 ("CLK: Add Loongson1C clock support")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman

clk: renesas: mstp: Support 8-bit registers for r7s72100

2017-01-12T10:39:28+00:00

commit e2a33c34ddff22ee208d80abdd12b88a98d6cb60 upstream.

The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.

Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Kuninori Morimoto 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: imx31: fix rewritten input argument of mx31_clocks_init()

2017-01-12T10:39:27+00:00

commit bae203d58b7dce89664071b3fafe20cedaa3e4f6 upstream.

Function mx31_clocks_init() is called during clock intialization on
legacy boards with reference clock frequency passed as its input
argument, this can be verified by examination of the function
declaration found in arch/arm/mach-imx/common.h and actual function
users which include that header file.

Inside CCF driver the function ignores its input argument, by chance
the used value in the function body is the same as input arguments on
side of all callers.

Fixes: d9388c843237 ("clk: imx31: Do not call mxc_timer_init twice when booting with DT")
Signed-off-by: Vladimir Zapolskiy 
Reviewed-by: Uwe Kleine-König 
Acked-by: Stephen Boyd 
Signed-off-by: Shawn Guo 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks

2017-01-12T10:39:27+00:00

commit 0f6f9302b819ca352cfd4f42c18ec08d521f9cae upstream.

The audio module clocks are supposed to be set according to the sample
rate of the audio stream. The audio PLL provides the clock signal for
these module clocks, and only it is freely tunable.

Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
properly tune the clock rate.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman