linux-toradex.git/drivers/clk, branch v5.0-rc7

clk: qcom: gcc: Use active only source for CPUSS clocks

2019-01-24T19:41:48+00:00

The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL
clock and needs to vote on the active only source of XO, so as to keep
the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has
the same requirement.

Signed-off-by: Taniya Das 
Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Signed-off-by: Stephen Boyd

clk: ti: Fix error handling in ti_clk_parse_divider_data()

2019-01-24T19:23:32+00:00

The ti_clk_parse_divider_data() function is only called from
_get_div_table_from_setup().  That function doesn't look at the return
value but instead looks at the "*table" pointer.  In this case, if the
kcalloc() fails then *table is NULL (which means success).  It should
instead be an error pointer.

The ti_clk_parse_divider_data() function has two callers.  One checks
for errors and the other doesn't.  I have fixed it so now both handle
errors.

Fixes: 4f6be5655dc9 ("clk: ti: divider: add driver internal API for parsing divider data")
Signed-off-by: Dan Carpenter 
Acked-by: Tero Kristo 
Signed-off-by: Stephen Boyd

clk: imx: Fix fractional clock set rate computation

2019-01-24T19:17:28+00:00

Before multiplying by PLL_FRAC_DENOM, the temp64 needs to be
 temp64 = rate * 2 - divfi * parent_rate * 8, instead of:
 temp64 = (rate * 2 - divfi) * parent_rate

Fixes: 6209624b9a5c1e ("clk: imx: Add fractional PLL output clock")
Signed-off-by: Abel Vesa 
Signed-off-by: Stephen Boyd

clk: Remove global clk traversal on fetch parent index

2019-01-24T19:13:28+00:00

It's not required to traverse the entire clk tree when the parents array
contains a NULL value. We already have the parent clk_core pointer, so
we can just compare the parent->name and parent_names[i] pointers.

This can be a substantial power improvement in cases where the parent
clk isn't known and that clk is never registered, because a mux having
an unregistered parent name may traverse the clk tree on every
clk_set_rate() call in clk_mux_determine_rate_flags(). This can happen
hundreds of times a second for CPU clks.

This patch is the combination of reverting commit 470b5e2f97cf ("clk:
simplify clk_fetch_parent_index() function") and optimizing the
resulting code to never call __clk_lookup() because we already have the
clk_core pointer we're looking for. That optimization went unnoticed
even after commit da0f0b2c3ad2 ("clk: Correct lookup logic in
clk_fetch_parent_index()") tried to optimize this path.

Signed-off-by: Derek Basehore 
[sboyd@kernel.org: More description in commit text]
Signed-off-by: Stephen Boyd

Revert "clk: mmp2: add SP clock"

2019-01-24T18:55:32+00:00

It seems that the kernel has no business managing this clock: once the SP
clock is disabled, it's not sufficient to just enable in order to bring the
SP core back up. Just let the firmware keep it enabled and don't expose it
to drivers.

This reverts commit fc27c2394d96fd19854b7e2d3f0e60df0d86fc90.

Link: https://lore.kernel.org/lkml/154783267051.169631.3197836544646625747@swboyd.mtv.corp.google.com/
Signed-off-by: Lubomir Rintel 
Signed-off-by: Stephen Boyd

clk: socfpga: stratix10: fix naming convention for the fixed-clocks

2019-01-15T20:58:38+00:00

The fixed clocks in the DTS file have a hyphen, but the clock driver has
the fixed clocks using underbar. Thus the clock driver cannot detect the
other fixed clocks correctly. Change the fixed clock names to a hyphen.

Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen 
Signed-off-by: Stephen Boyd

clk: socfpga: stratix10: fix rate calculation for pll clocks

2019-01-11T23:41:02+00:00

The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen 
Signed-off-by: Stephen Boyd

clk: qcom: Select QCOM_GDSC with MSM_GCC_8998

2019-01-11T18:39:15+00:00

If QCOM_GDSC is disabled, gdsc_register() returns -ENOSYS, which causes
gcc_msm8998_probe() to fail. Select QCOM_GDSC to solve the problem.

gcc-msm8998: probe of 100000.clock-controller failed with error -38

Signed-off-by: Marc Gonzalez 
Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: Stephen Boyd

clk: vc5: Abort clock configuration without upstream clock

2019-01-09T18:53:58+00:00

In case the upstream clock are not set, which can happen in case the
VC5 has no valid upstream clock, the $src variable is used uninited
by regmap_update_bits(). Check for this condition and return -EINVAL
in such case.

Note that in case the VC5 has no valid upstream clock, the VC5 can
not operate correctly. That is a hardware property of the VC5. The
internal oscilator present in some VC5 models is also considered
upstream clock.

Signed-off-by: Marek Vasut 
Cc: Alexey Firago 
Cc: Laurent Pinchart 
Cc: Stephen Boyd 
Cc: linux-renesas-soc@vger.kernel.org
[sboyd@kernel.org: Added comment about probe preventing this from
happening in the first place]
Signed-off-by: Stephen Boyd

clk: sysfs: fix invalid JSON in clk_dump

2019-01-09T18:45:03+00:00

Add a missing comma so that the output is valid JSON format again.

Fixes: 9fba738a53dd ("clk: add duty cycle support")
Signed-off-by: Lubomir Rintel 
Signed-off-by: Stephen Boyd