linux-toradex.git/drivers/clk, branch v6.16-rc4 Linux kernel for Apalis and Colibri modules Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2025-05-30T16:15:40+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-05-30T16:15:40+00:00 9f32a03e3e0d372c520d829dd4da6022fe88832a Pull clk updates from Stephen Boyd: "This has been a semi-quiet cycle. The core framework remains unchanged this time around. In terms of shiny new code though, we have support for the SpacemiT K1 SoC, Sophgo SG2044, and T-HEAD TH1520 VO clk drivers joining the usual silicon players like Qualcomm, Samsung, Allwinner, and Renesas. Surprisingly, the Qualcomm pile was smaller than usual but that is likely because they put one SoC support inside a driver for a different SoC that is very similar. Other than all those new clk drivers there are the usual clk data updates to fix parents, frequency tables, and add missing clks along with some Kconfig changes to make compile testing simpler and even more DT binding conversions to boot. The exciting part is still the new SoC support like SpacemiT and Sophgo support though, which really dominate the diffstat because they introduce a whole new silicon vendor clk driver. New Drivers: - Camera clock controller driver for Qualcomm QCS8300 - DE (display engine) 3.3 clocks on Allwinner H616 - Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers - Video Output (VO) subsystem clk controller in the T-HEAD TH1520 SoC - Clock driver for Sophgo SG2044 - Clock driver for SpacemiT K1 SoC - Renesas RZ/V2N (R9A09G056) SoC clk driver Updates: - Correct data in various SoC clk drivers - Allow clkaN to be optional in the Qualcomm RPMh clock controller driver if command db doesn't define it - Change Kconfig options to not enable by default during compile testing - Add missing clks in various SoC clk drivers - Remove some duplicate clk DT bindings and convert some more to YAML" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: rpmh: make clkaN optional clk: qcom: Add support for Camera Clock Controller on QCS8300 clk: rockchip: rk3528: add slab.h header include clk: rockchip: rk3576: add missing slab.h include clk: meson: Do not enable by default during compile testing clk: meson-g12a: add missing fclk_div2 to spicc clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz clk: rockchip: rename gate-grf clk file clk: rockchip: rename branch_muxgrf to branch_grf_mux clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support dt-bindings: allwinner: add H616 DE33 clock binding clk: samsung: correct clock summary for hsi1 block dt-bindings: clock: add SM6350 QCOM video clock bindings clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks clk: sunxi-ng: h616: Add LVDS reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset clk: rockchip: rk3036: mark ddrphy as critical clk: rockchip: rk3036: fix implementation of usb480m clock mux ... 
Pull clk updates from Stephen Boyd:
 "This has been a semi-quiet cycle. The core framework remains unchanged
  this time around.

  In terms of shiny new code though, we have support for the SpacemiT K1
  SoC, Sophgo SG2044, and T-HEAD TH1520 VO clk drivers joining the usual
  silicon players like Qualcomm, Samsung, Allwinner, and Renesas.

  Surprisingly, the Qualcomm pile was smaller than usual but that is
  likely because they put one SoC support inside a driver for a
  different SoC that is very similar.

  Other than all those new clk drivers there are the usual clk data
  updates to fix parents, frequency tables, and add missing clks along
  with some Kconfig changes to make compile testing simpler and even
  more DT binding conversions to boot.

  The exciting part is still the new SoC support like SpacemiT and
  Sophgo support though, which really dominate the diffstat because they
  introduce a whole new silicon vendor clk driver.

  New Drivers:
   - Camera clock controller driver for Qualcomm QCS8300
   - DE (display engine) 3.3 clocks on Allwinner H616
   - Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers
   - Video Output (VO) subsystem clk controller in the T-HEAD TH1520 SoC
   - Clock driver for Sophgo SG2044
   - Clock driver for SpacemiT K1 SoC
   - Renesas RZ/V2N (R9A09G056) SoC clk driver

  Updates:
   - Correct data in various SoC clk drivers
   - Allow clkaN to be optional in the Qualcomm RPMh clock controller
     driver if command db doesn't define it
   - Change Kconfig options to not enable by default during compile
     testing
   - Add missing clks in various SoC clk drivers
   - Remove some duplicate clk DT bindings and convert some more to
     YAML"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
  clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
  clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
  clk: qcom: rpmh: make clkaN optional
  clk: qcom: Add support for Camera Clock Controller on QCS8300
  clk: rockchip: rk3528: add slab.h header include
  clk: rockchip: rk3576: add missing slab.h include
  clk: meson: Do not enable by default during compile testing
  clk: meson-g12a: add missing fclk_div2 to spicc
  clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
  clk: rockchip: rename gate-grf clk file
  clk: rockchip: rename branch_muxgrf to branch_grf_mux
  clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
  dt-bindings: allwinner: add H616 DE33 clock binding
  clk: samsung: correct clock summary for hsi1 block
  dt-bindings: clock: add SM6350 QCOM video clock bindings
  clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
  clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
  clk: rockchip: rk3036: mark ddrphy as critical
  clk: rockchip: rk3036: fix implementation of usb480m clock mux
  ...
Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next 2025-05-29T07:30:39+00:00 Stephen Boyd sboyd@kernel.org 2025-05-29T07:30:39+00:00 63bfd78aae9a90210b0d369bb2836cca90402a95 * clk-amlogic: clk: meson: Do not enable by default during compile testing clk: meson-g12a: add missing fclk_div2 to spicc * clk-allwinner: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support dt-bindings: allwinner: add H616 DE33 clock binding clk: sunxi-ng: h616: Add LVDS reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset clk: sunxi: Do not enable by default during compile testing clk: sunxi-ng: Do not enable by default during compile testing * clk-rockchip: clk: rockchip: rk3528: add slab.h header include clk: rockchip: rk3576: add missing slab.h include clk: rockchip: rename gate-grf clk file clk: rockchip: rename branch_muxgrf to branch_grf_mux clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks clk: rockchip: rk3036: mark ddrphy as critical clk: rockchip: rk3036: fix implementation of usb480m clock mux dt-bindings: clock: rk3036: add SCLK_USB480M clock-id clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region clk: rockchip: Support MMC clocks in GRF region dt-bindings: clock: Add GRF clock definition for RK3528 clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576 clk: rockchip: introduce GRF gates clk: rockchip: introduce auxiliary GRFs dt-bindings: clock: rk3576: add IOC gated clocks clk: rockchip: rk3568: Add PLL rate for 33.3MHz clk: rockchip: Drop empty init callback for rk3588 PLL type clk: rockchip: rk3588: Add PLL rate for 1500 MHz * clk-qcom: clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: rpmh: make clkaN optional clk: qcom: Add support for Camera Clock Controller on QCS8300 clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz dt-bindings: clock: add SM6350 QCOM video clock bindings clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: Fix missing error check for dev_pm_domain_attach() 
* clk-amlogic:
  clk: meson: Do not enable by default during compile testing
  clk: meson-g12a: add missing fclk_div2 to spicc

* clk-allwinner:
  clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
  dt-bindings: allwinner: add H616 DE33 clock binding
  clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
  clk: sunxi: Do not enable by default during compile testing
  clk: sunxi-ng: Do not enable by default during compile testing

* clk-rockchip:
  clk: rockchip: rk3528: add slab.h header include
  clk: rockchip: rk3576: add missing slab.h include
  clk: rockchip: rename gate-grf clk file
  clk: rockchip: rename branch_muxgrf to branch_grf_mux
  clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
  clk: rockchip: rk3036: mark ddrphy as critical
  clk: rockchip: rk3036: fix implementation of usb480m clock mux
  dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
  clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region
  clk: rockchip: Support MMC clocks in GRF region
  dt-bindings: clock: Add GRF clock definition for RK3528
  clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
  clk: rockchip: introduce GRF gates
  clk: rockchip: introduce auxiliary GRFs
  dt-bindings: clock: rk3576: add IOC gated clocks
  clk: rockchip: rk3568: Add PLL rate for 33.3MHz
  clk: rockchip: Drop empty init callback for rk3588 PLL type
  clk: rockchip: rk3588: Add PLL rate for 1500 MHz

* clk-qcom:
  clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
  clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
  clk: qcom: rpmh: make clkaN optional
  clk: qcom: Add support for Camera Clock Controller on QCS8300
  clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
  dt-bindings: clock: add SM6350 QCOM video clock bindings
  clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: Fix missing error check for dev_pm_domain_attach()
Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next 2025-05-29T07:30:28+00:00 Stephen Boyd sboyd@kernel.org 2025-05-29T07:30:28+00:00 3e515fc8601a1ea85becf7d990ad8700e012a70a * clk-socfpga: clk: socfpga: stratix10: Optimize local variables clk: socfpga: clk-pll: Optimize local variables * clk-sophgo: clk: sophgo: Add clock controller support for SG2044 SoC clk: sophgo: Add PLL clock controller support for SG2044 SoC dt-bindings: clock: sophgo: add clock controller for SG2044 dt-bindings: soc: sophgo: Add SG2044 top syscon device clk: sophgo: Add support for newly added precise compatible dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC * clk-thead: clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC dt-bindings: clock: thead: Add TH1520 VO clock controller * clk-samsung: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function 
* clk-socfpga:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables

* clk-sophgo:
  clk: sophgo: Add clock controller support for SG2044 SoC
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  dt-bindings: clock: sophgo: add clock controller for SG2044
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  clk: sophgo: Add support for newly added precise compatible
  dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC

* clk-thead:
  clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
  dt-bindings: clock: thead: Add TH1520 VO clock controller

* clk-samsung:
  clk: samsung: correct clock summary for hsi1 block
  clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
  clk: samsung: exynosautov920: add cpucl1/2 clock support
  dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
  clk: samsung: exynosautov920: add cpucl0 clock support
  dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
  clk: samsung: Use samsung CCF common function
Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into clk-next 2025-05-29T07:30:17+00:00 Stephen Boyd sboyd@kernel.org 2025-05-29T07:30:17+00:00 7459da16c9a4bf324e7f5789f296e02e7bc24b68 * clk-bindings: dt-bindings: clock: Drop st,stm32h7-rcc.txt dt-bindings: clock: convert bcm2835-aux-clock to yaml dt-bindings: clock: Drop maxim,max77686.txt dt-bindings: clock: convert vf610-clock.txt to yaml format * clk-renesas: (26 commits) clk: renesas: r9a09g047: Add XSPI clock/reset clk: renesas: r9a09g047: Add support for xspi mux and divider dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks clk: renesas: Use str_on_off() helper clk: renesas: r9a09g057: Add clock and reset entries for USB2 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h: Support static dividers without RMW clk: renesas: rzv2h: Add macro for defining static dividers clk: renesas: rzv2h: Add support for static mux clocks clk: renesas: r9a09g047: Add clock and reset entries for GE3D clk: renesas: rzv2h: Fix a typo clk: renesas: rzv2h: Add support for RZ/V2N SoC clk: renesas: rzv2h: Sort compatible list based on SoC part number dt-bindings: pinctrl: renesas: Document RZ/V2N SoC dt-bindings: clock: renesas: Document RZ/V2N SoC CPG dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() ... * clk-spacemit: clk: spacemit: k1: Add TWSI8 bus and function clocks clk: spacemit: Add clock support for SpacemiT K1 SoC dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon * clk-cleanup: clk: test: Forward-declare struct of_phandle_args in kunit/clk.h clk: davinci: Use of_get_available_child_by_name() clk: bcm: rpi: Add NULL check in raspberrypi_clk_register() clk: bcm: rpi: Drop module alias clk: bcm: kona: Remove unused scaled_div_build 
* clk-bindings:
  dt-bindings: clock: Drop st,stm32h7-rcc.txt
  dt-bindings: clock: convert bcm2835-aux-clock to yaml
  dt-bindings: clock: Drop maxim,max77686.txt
  dt-bindings: clock: convert vf610-clock.txt to yaml format

* clk-renesas: (26 commits)
  clk: renesas: r9a09g047: Add XSPI clock/reset
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
  clk: renesas: Use str_on_off() helper
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  ...

* clk-spacemit:
  clk: spacemit: k1: Add TWSI8 bus and function clocks
  clk: spacemit: Add clock support for SpacemiT K1 SoC
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon

* clk-cleanup:
  clk: test: Forward-declare struct of_phandle_args in kunit/clk.h
  clk: davinci: Use of_get_available_child_by_name()
  clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()
  clk: bcm: rpi: Drop module alias
  clk: bcm: kona: Remove unused scaled_div_build
Merge tag 'sunxi-clk-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes 2025-05-18T03:46:38+00:00 Stephen Boyd sboyd@kernel.org 2025-05-18T03:46:38+00:00 6a56880562d470b7bbdd1d955ff3fad4ad73a74f Pull Allwinner clk driver fixes from Chen-Yu Tsai: Only two changes: - Fix the order of arguments in clk macro for SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT that was recently introduced in v6.15-rc1 - Add missing post-divider for D1 MMC clocks to correct halved performance * tag 'sunxi-clk-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: d1: Add missing divider for MMC mod clocks clk: sunxi-ng: fix order of arguments in clock macro 
Pull Allwinner clk driver fixes from Chen-Yu Tsai:

Only two changes:

- Fix the order of arguments in clk macro for
  SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT that was recently introduced in
  v6.15-rc1

- Add missing post-divider for D1 MMC clocks to correct halved
  performance

* tag 'sunxi-clk-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: d1: Add missing divider for MMC mod clocks
  clk: sunxi-ng: fix order of arguments in clock macro
clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks 2025-05-18T00:28:40+00:00 Taniya Das quic_tdas@quicinc.com 2025-04-14T09:00:41+00:00 201bf08ba9e26eeb0a96ba3fd5c026f531b31aed Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. This is required for the MCQ feature of UFS. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-2-67b5529b9b5d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to
force the core on signal to remain active during halt state of the clk.
If force mem core bit of the clock is not set, the memories of the
subsystem will not retain the logic across power states. This is
required for the MCQ feature of UFS.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-2-67b5529b9b5d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 2025-05-18T00:28:40+00:00 Taniya Das quic_tdas@quicinc.com 2025-04-14T09:00:40+00:00 da94a81ea6c6f1cd2f389c5631e33c145ac7b35b Update the force mem core bit for UFS AXI clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. This is required for the MCQ feature of the UFS driver. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-1-67b5529b9b5d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Update the force mem core bit for UFS AXI clock to force the core on
signal to remain active during halt state of the clk. If force mem
core bit of the clock is not set, the memories of the subsystem will
not retain the logic across power states. This is required for the MCQ
feature of the UFS driver.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-1-67b5529b9b5d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: rpmh: make clkaN optional 2025-05-18T00:26:35+00:00 Pengyu Luo mitltlatltl@gmail.com 2025-04-13T17:22:04+00:00 166e65bc6ce317be41368d9340b870edbdbaa2aa On SM8650, clkaN are missing in cmd-db for some specific devices. This caused a boot failure. Printing log during initramfs phase, I found [ 0.053281] clk-rpmh 17a00000.rsc:clock-controller: missing RPMh resource address for clka1 Adding the optional property to avoid probing failure which causes countless deferred probe. In the downstream tree,similar workarounds are introduced for SM7635, SM8550, SM8635, SM8650, SM8750. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Link: https://lore.kernel.org/r/20250413172205.175789-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
On SM8650, clkaN are missing in cmd-db for some specific devices. This
caused a boot failure. Printing log during initramfs phase, I found

[    0.053281] clk-rpmh 17a00000.rsc:clock-controller: missing RPMh resource address for clka1

Adding the optional property to avoid probing failure which causes
countless deferred probe. In the downstream tree,similar workarounds
are introduced for SM7635, SM8550, SM8635, SM8650, SM8750.

Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Link: https://lore.kernel.org/r/20250413172205.175789-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: Add support for Camera Clock Controller on QCS8300 2025-05-17T23:59:19+00:00 Imran Shaik quic_imrashai@quicinc.com 2025-03-27T10:02:27+00:00 1003cea3c7764ae582302c395f82e1cf7e5cd8f6 The QCS8300 Camera clock controller is a derivative of SA8775P, but has few additional clocks and offset differences. Hence, add support for QCS8300 Camera clock controller by extending the SA8775P CamCC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250327-qcs8300-mm-patches-v6-1-b3fbde2820a6@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
The QCS8300 Camera clock controller is a derivative of SA8775P, but has
few additional clocks and offset differences. Hence, add support for
QCS8300 Camera clock controller by extending the SA8775P CamCC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250327-qcs8300-mm-patches-v6-1-b3fbde2820a6@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: rockchip: rk3528: add slab.h header include 2025-05-15T12:49:05+00:00 Heiko Stuebner heiko@sntech.de 2025-05-15T08:26:52+00:00 276036283716b9135525b195675ea42801bde204 The newly added GRF types introduced kzalloc usage into the rk3528. At least for the similar rk3576 driver, the kernel-test-robot reported the missing prototype, which warranted adding a slab.h include. While it did not complain about the rk3528, so the header might be included "accidentially" right now, add a real include to make sure we keep it included in the future. Fixes: 306d2f5ddaa7 ("clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250515082652.2503063-2-heiko@sntech.de 
The newly added GRF types introduced kzalloc usage into the rk3528.
At least for the similar rk3576 driver, the kernel-test-robot reported the
missing prototype, which warranted adding a slab.h include.

While it did not complain about the rk3528, so the header might be included
"accidentially" right now, add a real include to make sure we keep it
included in the future.

Fixes: 306d2f5ddaa7 ("clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250515082652.2503063-2-heiko@sntech.de