<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/clocksource/Makefile, branch v3.14.57</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2014-01-24T02:40:49+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2014-01-24T02:40:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=dfd10e7ae60c6c1b24b5d601744b4fd1ecab2f31'/>
<id>dfd10e7ae60c6c1b24b5d601744b4fd1ecab2f31</id>
<content type='text'>
Pull ARM SoC platform changes from Olof Johansson:
 "New core SoC-specific changes.

  New platforms:
   * Introduction of a vendor, Hisilicon, and one of their SoCs with
     some random numerical product name.
   * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
     i.e. !MMU).
   * Marvell Berlin series of SoCs, which include the one in Chromecast.
   * MOXA platform support, ARM9-based platform used mostly in
     industrial products
   * Support for Freescale's i.MX50 SoC.

  Other work:
   * Renesas work for new platforms and drivers, and conversion over to
     more multiplatform-friendly device registration schemes.
   * SMP support for Allwinner sunxi platforms.
   * ... plus a bunch of other stuff across various platforms"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
  ARM: tegra: fix tegra_powergate_sequence_power_up() inline
  ARM: msm_defconfig: Update for multi-platform
  ARM: msm: Move MSM's DT based hardware to multi-platform support
  ARM: msm: Only build timer.c if required
  ARM: msm: Only build clock.c on proc_comm based platforms
  ARM: ux500: Enable system suspend with WFI support
  ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
  ARM: shmobile: r8a7790: Fix I2C controller names
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull ARM SoC platform changes from Olof Johansson:
 "New core SoC-specific changes.

  New platforms:
   * Introduction of a vendor, Hisilicon, and one of their SoCs with
     some random numerical product name.
   * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
     i.e. !MMU).
   * Marvell Berlin series of SoCs, which include the one in Chromecast.
   * MOXA platform support, ARM9-based platform used mostly in
     industrial products
   * Support for Freescale's i.MX50 SoC.

  Other work:
   * Renesas work for new platforms and drivers, and conversion over to
     more multiplatform-friendly device registration schemes.
   * SMP support for Allwinner sunxi platforms.
   * ... plus a bunch of other stuff across various platforms"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
  ARM: tegra: fix tegra_powergate_sequence_power_up() inline
  ARM: msm_defconfig: Update for multi-platform
  ARM: msm: Move MSM's DT based hardware to multi-platform support
  ARM: msm: Only build timer.c if required
  ARM: msm: Only build clock.c on proc_comm based platforms
  ARM: ux500: Enable system suspend with WFI support
  ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
  ARM: shmobile: r8a7790: Fix I2C controller names
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>rename ARCH_BCM to ARCH_BCM_MOBILE (clocksource)</title>
<updated>2013-12-13T16:36:22+00:00</updated>
<author>
<name>Christian Daudt</name>
<email>bcm@fixthebug.org</email>
</author>
<published>2013-09-23T17:20:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=047ef2fa4e687b6c0d4e7d47b8a184147151482c'/>
<id>047ef2fa4e687b6c0d4e7d47b8a184147151482c</id>
<content type='text'>
Currently ARCH_BCM has been used for Broadcom
Mobile V7 based SoCs. In order to allow other Broadcom
SoCs to also use mach-bcm directory and files, this patch
renames the original ARCH_BCM to ARCH_BCM_MOBILE, and
uses ARCH_BCM to define any Broadcom chip residing
in mach-bcm directory.

Signed-off-by: Christian Daudt &lt;bcm@fixthebug.org&gt;
Acked-by: Olof Johansson &lt;olof@lixom.net&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently ARCH_BCM has been used for Broadcom
Mobile V7 based SoCs. In order to allow other Broadcom
SoCs to also use mach-bcm directory and files, this patch
renames the original ARCH_BCM to ARCH_BCM_MOBILE, and
uses ARCH_BCM to define any Broadcom chip residing
in mach-bcm directory.

Signed-off-by: Christian Daudt &lt;bcm@fixthebug.org&gt;
Acked-by: Olof Johansson &lt;olof@lixom.net&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clocksource: Add Allwinner SoCs HS timers driver</title>
<updated>2013-12-11T10:37:50+00:00</updated>
<author>
<name>Maxime Ripard</name>
<email>maxime.ripard@free-electrons.com</email>
</author>
<published>2013-11-07T11:01:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=67905540e8b8eaf51e621cfd2ef15641d6d5b9a7'/>
<id>67905540e8b8eaf51e621cfd2ef15641d6d5b9a7</id>
<content type='text'>
Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.

The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.

[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
		alphabetically"

Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Tested-by: Emilio López &lt;emilio@elopez.com.ar&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.

The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.

[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
		alphabetically"

Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Tested-by: Emilio López &lt;emilio@elopez.com.ar&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clocksource: Provide timekeeping for efm32 SoCs</title>
<updated>2013-10-22T20:36:33+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2013-10-03T19:56:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9c9b781804e0a278e258f81dfc31c50f80867730'/>
<id>9c9b781804e0a278e258f81dfc31c50f80867730</id>
<content type='text'>
An efm32 features 4 16-bit timers with a 10-bit prescaler. This driver
provides clocksource and clock event device using one timer instance
each.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
An efm32 features 4 16-bit timers with a 10-bit prescaler. This driver
provides clocksource and clock event device using one timer instance
each.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: clocksource: Add support for MOXA ART SoCs</title>
<updated>2013-07-18T13:27:47+00:00</updated>
<author>
<name>Jonas Jensen</name>
<email>jonas.jensen@gmail.com</email>
</author>
<published>2013-07-17T08:04:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=07862c1cd6675cde2dd4bd64e64d704ea2185b79'/>
<id>07862c1cd6675cde2dd4bd64e64d704ea2185b79</id>
<content type='text'>
This patch adds an clocksource driver for the main timer(s)
found on MOXA ART SoCs.

The MOXA ART SoC provides three separate timers with individual
count/load/match registers, two are used here:

TIMER1: clockevents, used to support oneshot and periodic events
TIMER2: set up as a free running counter, used as clocksource

Timers are preconfigured by bootloader to count down and interrupt
on match or zero. Count increments every APB clock cycle and is
automatically reloaded when it reaches zero.

Signed-off-by: Jonas Jensen &lt;jonas.jensen@gmail.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds an clocksource driver for the main timer(s)
found on MOXA ART SoCs.

The MOXA ART SoC provides three separate timers with individual
count/load/match registers, two are used here:

TIMER1: clockevents, used to support oneshot and periodic events
TIMER2: set up as a free running counter, used as clocksource

Timers are preconfigured by bootloader to count down and interrupt
on match or zero. Count increments every APB clock cycle and is
automatically reloaded when it reaches zero.

Signed-off-by: Jonas Jensen &lt;jonas.jensen@gmail.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clocksource: arm_global_timer: Add ARM global timer support</title>
<updated>2013-07-03T15:30:57+00:00</updated>
<author>
<name>Stuart Menefy</name>
<email>stuart.menefy@st.com</email>
</author>
<published>2013-06-26T11:48:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c1b40e447af8695666d4c11cfec4a7407e6a124d'/>
<id>c1b40e447af8695666d4c11cfec4a7407e6a124d</id>
<content type='text'>
This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions of the system timer and the local timer in an SMP system.

The global timer has the following features:
    The global timer is a 64-bit incrementing counter with an
auto-incrementing feature. It continues incrementing after sending
interrupts. The global timer is memory mapped in the private memory
region.
    The global timer is accessible to all Cortex-A9 processors in the
cluster. Each Cortex-A9 processor has a private 64-bit comparator that
is used to assert a private interrupt when the global timer has reached
the comparator value. All the Cortex-A9 processors in a design use the
banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
Controller as a Private Peripheral Interrupt. The global timer is
clocked by PERIPHCLK.

Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@st.com&gt;
CC: Arnd Bergmann &lt;arnd@arndb.de&gt;
CC: Rob Herring &lt;robherring2@gmail.com&gt;
CC: Linus Walleij &lt;linus.walleij@linaro.org&gt;
CC: Will Deacon &lt;will.deacon@arm.com&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions of the system timer and the local timer in an SMP system.

The global timer has the following features:
    The global timer is a 64-bit incrementing counter with an
auto-incrementing feature. It continues incrementing after sending
interrupts. The global timer is memory mapped in the private memory
region.
    The global timer is accessible to all Cortex-A9 processors in the
cluster. Each Cortex-A9 processor has a private 64-bit comparator that
is used to assert a private interrupt when the global timer has reached
the comparator value. All the Cortex-A9 processors in a design use the
banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
Controller as a Private Peripheral Interrupt. The global timer is
clocked by PERIPHCLK.

Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@st.com&gt;
CC: Arnd Bergmann &lt;arnd@arndb.de&gt;
CC: Rob Herring &lt;robherring2@gmail.com&gt;
CC: Linus Walleij &lt;linus.walleij@linaro.org&gt;
CC: Will Deacon &lt;will.deacon@arm.com&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clocksource: Add Marvell Orion SoC timer</title>
<updated>2013-07-02T13:01:45+00:00</updated>
<author>
<name>Sebastian Hesselbarth</name>
<email>sebastian.hesselbarth@gmail.com</email>
</author>
<published>2013-06-11T06:38:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0c1dcfd53b1066c411d3885cf8156abf59694360'/>
<id>0c1dcfd53b1066c411d3885cf8156abf59694360</id>
<content type='text'>
This patch add a DT enabled driver for timers found on Marvell Orion SoCs
(Kirkwood, Dove, Orion5x, and Discovery Innovation). It installs a free-
running clocksource on timer0 and a clockevent source on timer1.
Corresponding device tree documentation is also added.

Signed-off-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Tested-by: Ezequiel Garcia &lt;ezequiel.garcia@free-electrons.com&gt;
Tested-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch add a DT enabled driver for timers found on Marvell Orion SoCs
(Kirkwood, Dove, Orion5x, and Discovery Innovation). It installs a free-
running clocksource on timer0 and a clockevent source on timer1.
Corresponding device tree documentation is also added.

Signed-off-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Tested-by: Ezequiel Garcia &lt;ezequiel.garcia@free-electrons.com&gt;
Tested-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clocksource: Add generic dummy timer driver</title>
<updated>2013-06-24T20:27:37+00:00</updated>
<author>
<name>Mark Rutland</name>
<email>mark.rutland@arm.com</email>
</author>
<published>2013-06-03T20:33:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=064706514ec3fea740c2656e03c4f01f6a551ac4'/>
<id>064706514ec3fea740c2656e03c4f01f6a551ac4</id>
<content type='text'>
Several architectures have a dummy timer driver tightly coupled with
their broadcast code to support machines without cpu-local timers (or
where there is a lack of driver support).

Since 12ad100046: "clockevents: Add generic timer broadcast function"
it's been possible to write broadcast-capable timer drivers decoupled
from the broadcast mechanism. We can use this functionality to implement
a generic dummy timer driver that can be shared by all architectures
with generic tick broadcast (ARCH_HAS_TICK_BROADCAST).

This patch implements a generic dummy timer using this facility.

[sboyd: Make percpu data static, use __this_cpu_ptr(), move to
        early_initcall to properly register on each CPU, only
	register if more than one CPU possible]

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;,
Cc: John Stultz &lt;john.stultz@linaro.org&gt;
Cc: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1370291642-13259-3-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Several architectures have a dummy timer driver tightly coupled with
their broadcast code to support machines without cpu-local timers (or
where there is a lack of driver support).

Since 12ad100046: "clockevents: Add generic timer broadcast function"
it's been possible to write broadcast-capable timer drivers decoupled
from the broadcast mechanism. We can use this functionality to implement
a generic dummy timer driver that can be shared by all architectures
with generic tick broadcast (ARCH_HAS_TICK_BROADCAST).

This patch implements a generic dummy timer using this facility.

[sboyd: Make percpu data static, use __this_cpu_ptr(), move to
        early_initcall to properly register on each CPU, only
	register if more than one CPU possible]

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;,
Cc: John Stultz &lt;john.stultz@linaro.org&gt;
Cc: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1370291642-13259-3-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clocksource: Add TI-Nspire timer support</title>
<updated>2013-06-06T15:23:13+00:00</updated>
<author>
<name>Daniel Tang</name>
<email>dt.tangr@gmail.com</email>
</author>
<published>2013-06-01T06:02:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=77ba83bb1bb1cdabd522d32536f8eee65a870145'/>
<id>77ba83bb1bb1cdabd522d32536f8eee65a870145</id>
<content type='text'>
This patch adds a clocksource/clockevent driver for the timer found on some
models in the TI-Nspire calculator series. The timer has two 16bit subtimers
within its memory mapped I/O interface but only the first can generate
interrupts. The first subtimer is used to generate clockevents but only if an
interrupt number and register is given.

The interrupt acknowledgement mechanism is a little strange because the
interrupt mask and acknowledge registers are located in another memory mapped
I/O peripheral. The address of this register is passed to the driver through
device tree bindings.

The second subtimer is used as a clocksource because it isn't capable of
generating an interrupt. This subtimer is always added.

Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Daniel Tang &lt;dt.tangr@gmail.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds a clocksource/clockevent driver for the timer found on some
models in the TI-Nspire calculator series. The timer has two 16bit subtimers
within its memory mapped I/O interface but only the first can generate
interrupts. The first subtimer is used to generate clockevents but only if an
interrupt number and register is given.

The interrupt acknowledgement mechanism is a little strange because the
interrupt mask and acknowledge registers are located in another memory mapped
I/O peripheral. The address of this register is passed to the driver through
device tree bindings.

The second subtimer is used as a clocksource because it isn't capable of
generating an interrupt. This subtimer is always added.

Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Daniel Tang &lt;dt.tangr@gmail.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clocksource: Add Freescale Vybrid pit timer support</title>
<updated>2013-06-06T15:23:13+00:00</updated>
<author>
<name>Jingchang Lu</name>
<email>b35083@freescale.com</email>
</author>
<published>2013-05-29T08:12:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c19672492d233e0012b60fbfa460ffac1381ee26'/>
<id>c19672492d233e0012b60fbfa460ffac1381ee26</id>
<content type='text'>
Add Freescale Vybrid Family period interrupt timer support.

Signed-off-by: Jingchang Lu &lt;b35083@freescale.com&gt;
Reviewed-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Acked-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
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Add Freescale Vybrid Family period interrupt timer support.

Signed-off-by: Jingchang Lu &lt;b35083@freescale.com&gt;
Reviewed-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Acked-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
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</content>
</entry>
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