linux-toradex.git/drivers/clocksource/Makefile, branch v5.11-rc5

clocksource/drivers/nps: Remove EZChip NPS clocksource driver

2020-12-03T18:16:18+00:00

NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !

Cc: Daniel Lezcano 
Cc: Thomas Gleixner 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Vineet Gupta 
Signed-off-by: Daniel Lezcano 
Link: https://lore.kernel.org/r/20201105212210.1891598-2-vgupta@synopsys.com

clocksource/drivers: Add CLINT timer driver

2020-08-20T17:57:29+00:00

We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
RISC-V NoMMU kernel).

The CLINT MMIO device provides three things:
1. 64bit free running counter register
2. 64bit per-CPU time compare registers
3. 32bit per-CPU inter-processor interrupt registers

Unlike other timer devices, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.

Signed-off-by: Anup Patel 
Tested-by: Emil Renner Berhing 
Acked-by: Daniel Lezcano 
Reviewed-by: Atish Patra 
Reviewed-by: Palmer Dabbelt 
Signed-off-by: Palmer Dabbelt

Merge tag 'mfd-next-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

2020-08-15T15:09:38+00:00

Pull MFD updates from Lee Jones:
 "Core Frameworks
   - Make better attempt at matching device with the correct OF node
   - Allow batch removal of hierarchical sub-devices

  New Drivers
   - Add STM32 Clocksource driver
   - Add support for Khadas System Control Microcontroller

  Driver Removal
   - Remove unused driver for TI's SMSC ECE1099

  New Device Support
   - Add support for Intel Emmitsburg PCH to Intel LPSS PCI
   - Add support for Intel Tiger Lake PCH-H to Intel LPSS PCI
   - Add support for Dialog DA revision to Dialog DA9063

  New Functionality
   - Add support for AXP803 to be probed by I2C

  Fix-ups
   - Numerous W=1 warning fixes
   - Device Tree changes (stm32-lptimer, gateworks-gsc, khadas,mcu, stmfx, cros-ec, j721e-system-controller)
   - Enabled Regmap 'fast I/O' in stm32-lptimer
   - Change BUG_ON to WARN_ON in arizona-core
   - Remove superfluous code/initialisation (madera, max14577)
   - Trivial formatting/spelling issues (madera-core, madera-i2c, da9055, max77693-private)
   - Switch to of_platform_populate() in sprd-sc27xx-spi
   - Expand out set/get brightness/pwm macros in lm3533-ctrlbank
   - Disable IRQs on suspend in motorola-cpcap
   - Clean-up error handling in intel_soc_pmic_mrfld
   - Ensure correct removal order of sub-devices in madera
   - Many s/HTTP/HTTPS/ link changes
   - Ensure name used with Regmap is unique in syscon

  Bug Fixes
   - Properly 'put' clock on unbind and error in arizona-core
   - Fix revision handling in da9063
   - Fix 'assignment of read-only location' error in kempld-core
   - Avoid using the Regmap API when atomic in rn5t618
   - Redefine volatile register description in rn5t618
   - Use locking to protect event handler in dln2"

* tag 'mfd-next-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (76 commits)
  mfd: syscon: Use a unique name with regmap_config
  mfd: Replace HTTP links with HTTPS ones
  mfd: dln2: Run event handler loop under spinlock
  mfd: madera: Improve handling of regulator unbinding
  mfd: mfd-core: Add mechanism for removal of a subset of children
  mfd: intel_soc_pmic_mrfld: Simplify the return expression of intel_scu_ipc_dev_iowrite8()
  mfd: max14577: Remove redundant initialization of variable current_bits
  mfd: rn5t618: Fix caching of battery related registers
  mfd: max77693-private: Drop a duplicated word
  mfd: da9055: pdata.h: Drop a duplicated word
  mfd: rn5t618: Make restart handler atomic safe
  mfd: kempld-core: Fix 'assignment of read-only location' error
  mfd: axp20x: Allow the AXP803 to be probed by I2C
  mfd: da9063: Add support for latest DA silicon revision
  mfd: da9063: Fix revision handling to correctly select reg tables
  dt-bindings: mfd: st,stmfx: Remove I2C unit name
  dt-bindings: mfd: ti,j721e-system-controller.yaml: Add J721e system controller
  mfd: motorola-cpcap: Disable interrupt for suspend
  mfd: smsc-ece1099: Remove driver
  mfd: core: Add OF_MFD_CELL_REG() helper
  ...

clocksource/drivers/ingenic: Add support for the Ingenic X1000 OST.

2020-07-23T14:58:09+00:00

X1000 and SoCs after X1000 (such as X1500 and X1830) had a separate
OST, it no longer belongs to TCU. This driver will register both a
clocksource and a sched_clock to the system.

Tested-by: 周正 (Zhou Zheng) 
Co-developed-by: 漆鹏振 (Qi Pengzhen) 
Signed-off-by: 漆鹏振 (Qi Pengzhen) 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Paul Cercueil 
Signed-off-by: Daniel Lezcano 
Link: https://lore.kernel.org/r/20200722171804.97559-3-zhouyanjie@wanyeetech.com

clocksource: Add Low Power STM32 timers driver

2020-06-18T10:19:58+00:00

Implement clock event driver using low power STM32 timers.
Low power timer counters running even when CPUs are stopped.
It could be used as clock event broadcaster to wake up CPUs but not like
a clocksource because each it rise an interrupt the counter restart from 0.

Low power timers have a 16 bits counter and a prescaler which allow to
divide the clock per power of 2 to up 128 to target a 32KHz rate.

Signed-off-by: Benjamin Gaignard 
Signed-off-by: Pascal Paillet 
Acked-by: Daniel Lezcano 
Signed-off-by: Lee Jones

clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support

2020-05-22T22:01:04+00:00

We can move the TI dmtimer clockevent and clocksource to live under
drivers/clocksource if we rely only on the clock framework, and handle
the module configuration directly in the clocksource driver based on the
device tree data.

This removes the early dependency with system timers to the interconnect
related code, and we can probe pretty much everything else later on at
the module_init level.

Let's first add a new driver for timer-ti-dm-systimer based on existing
arch/arm/mach-omap2/timer.c. Then let's start moving SoCs to probe with
device tree data while still keeping the old timer.c. And eventually we
can just drop the old timer.c.

Let's take the opportunity to switch to use readl/writel as pointed out
by Daniel Lezcano . This allows further
clean-up of the timer-ti-dm code the a lot of the shared helpers can
just become static to the non-syster related code.

Note the boards can optionally configure different timer source clocks
if needed with assigned-clocks and assigned-clock-parents.

Cc: linux-kernel@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: Daniel Lezcano 
Cc: Grygorii Strashko 
Cc: Keerthy 
Cc: Lokesh Vutla 
Cc: Rob Herring 
Cc: Tero Kristo 
Cc: Thomas Gleixner 
Signed-off-by: Tony Lindgren 
Signed-off-by: Daniel Lezcano 
Link: https://lore.kernel.org/r/20200507172330.18679-3-tony@atomide.com

clocksource: Add driver for the Ingenic JZ47xx OST

2020-02-27T08:37:29+00:00

OST is the OS Timer, a 64-bit timer/counter with buffered reading.

SoCs before the JZ4770 had (if any) a 32-bit OST; the JZ4770 and
JZ4780 have a 64-bit OST.

This driver will register both a clocksource and a sched_clock to the
system.

Signed-off-by: Maarten ter Huurne 
Signed-off-by: Paul Cercueil 
Tested-by: Mathieu Malaterre 
Tested-by: Artur Rojek 
Signed-off-by: Daniel Lezcano 
Link: https://lore.kernel.org/r/20200212180408.30872-1-paul@crapouillou.net

clocksource/drivers/timer-microchip-pit64b: Add Microchip PIT64B support

2020-01-16T18:06:57+00:00

Add driver for Microchip PIT64B timer. Timer could be used in continuous
mode or oneshot mode. The hardware has 2x32 bit registers for period
emulating a 64 bit timer. The LSB_PR and MSB_PR registers are used to
set the period value (compare value). TLSB and TMSB keeps the current
value of the counter. After a compare the TLSB and TMSB register resets.
The driver uses PIT64B timer for clocksource or clockevent. First
requested timer would be registered as clockevent, second one would be
registered as clocksource. Individual PIT64B hardware resources were
used for clocksource and clockevent to be able to support high resolution
timers with this hardware implementation.

Signed-off-by: Claudiu Beznea 
Signed-off-by: Daniel Lezcano 
Link: https://lore.kernel.org/r/1576235962-30123-3-git-send-email-claudiu.beznea@microchip.com

clocksource: Add a new timer-ingenic driver

2019-08-08T22:30:08+00:00

This driver handles the TCU (Timer Counter Unit) present on the Ingenic
JZ47xx SoCs, and provides the kernel with a system timer, a clocksource
and a sched_clock.

Signed-off-by: Paul Cercueil 
Tested-by: Mathieu Malaterre 
Tested-by: Artur Rojek 
Reviewed-by: Thomas Gleixner 
Signed-off-by: Paul Burton 
Cc: Ralf Baechle 
Cc: James Hogan 
Cc: Jonathan Corbet 
Cc: Lee Jones 
Cc: Arnd Bergmann 
Cc: Daniel Lezcano 
Cc: Michael Turquette 
Cc: Stephen Boyd 
Cc: Jason Cooper 
Cc: Marc Zyngier 
Cc: Rob Herring 
Cc: Mark Rutland 
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me

clocksource/drivers: Make Hyper-V clocksource ISA agnostic

2019-07-03T09:00:59+00:00

Hyper-V clock/timer code and data structures are currently mixed
in with other code in the ISA independent drivers/hv directory as
well as the ISA dependent Hyper-V code under arch/x86.

Consolidate this code and data structures into a Hyper-V clocksource driver
to better follow the Linux model. In doing so, separate out the ISA
dependent portions so the new clocksource driver works for x86 and for the
in-process Hyper-V on ARM64 code.

To start, move the existing clockevents code to create the new clocksource
driver. Update the VMbus driver to call initialization and cleanup routines
since the Hyper-V synthetic timers are not independently enumerated in
ACPI.

No behavior is changed and no new functionality is added.

Suggested-by: Marc Zyngier 
Signed-off-by: Michael Kelley 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Vitaly Kuznetsov 
Cc: "bp@alien8.de" 
Cc: "will.deacon@arm.com" 
Cc: "catalin.marinas@arm.com" 
Cc: "mark.rutland@arm.com" 
Cc: "linux-arm-kernel@lists.infradead.org" 
Cc: "gregkh@linuxfoundation.org" 
Cc: "linux-hyperv@vger.kernel.org" 
Cc: "olaf@aepfle.de" 
Cc: "apw@canonical.com" 
Cc: "jasowang@redhat.com" 
Cc: "marcelo.cerri@canonical.com" 
Cc: Sunil Muthuswamy 
Cc: KY Srinivasan 
Cc: "sashal@kernel.org" 
Cc: "vincenzo.frascino@arm.com" 
Cc: "linux-arch@vger.kernel.org" 
Cc: "linux-mips@vger.kernel.org" 
Cc: "linux-kselftest@vger.kernel.org" 
Cc: "arnd@arndb.de" 
Cc: "linux@armlinux.org.uk" 
Cc: "ralf@linux-mips.org" 
Cc: "paul.burton@mips.com" 
Cc: "daniel.lezcano@linaro.org" 
Cc: "salyzyn@android.com" 
Cc: "pcc@google.com" 
Cc: "shuah@kernel.org" 
Cc: "0x7f454c46@gmail.com" <0x7f454c46@gmail.com>
Cc: "linux@rasmusvillemoes.dk" 
Cc: "huw@codeweavers.com" 
Cc: "sfr@canb.auug.org.au" 
Cc: "pbonzini@redhat.com" 
Cc: "rkrcmar@redhat.com" 
Cc: "kvm@vger.kernel.org" 
Link: https://lkml.kernel.org/r/1561955054-1838-2-git-send-email-mikelley@microsoft.com