linux-toradex.git/drivers/clocksource/mtk_timer.c, branch v4.4.93

clocksource/drivers/mediatek: Use GPT as sched clock source

2015-10-15T15:41:58+00:00

When cpu is in deep idle, arch timer will stop counting. Setup GPT as
sched clock source so it can keep counting in idle.

Signed-off-by: Yingjoe Chen 
Signed-off-by: Daniel Lezcano 
Acked-by: Stephen Boyd 
Acked-by: Matthias Brugger

clockevents/drivers/mtk: Fix spurious interrupt leading to crash

2015-10-15T15:41:56+00:00

After analysis done by Yingjoe Chen, the timer appears to have a pending
interrupt when it is enabled.

Fix this by acknowledging the pending interrupt when enabling the timer
interrupt.

Signed-off-by: Daniel Lezcano 
Tested-by: Yingjoe Chen

clockevents/drivers/mtk: Migrate to new 'set-state' interface

2015-08-10T09:40:33+00:00

Migrate mtk driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.

This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.

Cc: Matthias Brugger 
Signed-off-by: Viresh Kumar 
Signed-off-by: Daniel Lezcano

clocksource: mtk: Fix race conditions in probe code

2015-02-25T09:28:49+00:00

We have two race conditions in the probe code which could lead to a null
pointer dereference in the interrupt handler.

The interrupt handler accesses the clockevent device, which may not yet be
registered.

First race condition happens when the interrupt handler gets registered before
the interrupts get disabled. The second race condition happens when the
interrupts get enabled, but the clockevent device is not yet registered.

Fix that by disabling the interrupts before we register the interrupt and enable
the interrupts after the clockevent device got registered.

Reported-by: Gongbae Park 
Signed-off-by: Matthias Brugger 
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano

clocksource: Add support for the Mediatek SoCs

2014-07-23T10:02:31+00:00

This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.

The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.

Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Purpose Timer block can be run with two clocks. A 13 MHz system
clock and the RTC clock running at 32 KHz. This implementation uses the system
clock with no clock source divider.

The interrupts are shared between the different timers and have to be read back
from a register. We just enable one interrupt for the clock event. The clock
event timer is used by all cores.

Signed-off-by: Matthias Brugger 
Acked-by: Thomas Gleixner 
Signed-off-by: Daniel Lezcano